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hd404369 series rev. 6.0 sept. 1998 description the hd404369 series is a 4-bit hmcs400-series microcomputer designed to increase program productivity and also incorporate large-capacity memory. each microcomputer has an a/d converter, input capture timer, 32-khz oscillator for clock, and four low-power dissipation modes. the hd404369 series includes nine chips: the hd404364, hd40a4364 with 4-kword rom; the HD404368, hd40a4368 with 8-kword rom; the hd4043612, hd40a43612 with 12-kword rom; the hd404369, hd40a4369 with 16-kword rom; the hd407a4369 with 16-kword prom. the hd40a4364, hd40a4368, hd40a43612, hd40a4369, and hd407a4369 are high speed versions (minimum instruction cycle time: 0.47 m s). the hd407a4369 is a prom version (ztat ? microcomputer). a program can be written to the prom by a prom writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (the ztat ? version is 27256-compatible.) features 512-digit 4-bit ram 54 i/o pins ? one input-only pin ? 53 input/output pins: 8 pins are intermediate-voltage nmos open drain with high-current pins (15 ma, max.) on-chip a/d converter (8-bit 12-channel) ? low power voltage 2.7 v to 6.0 v three timers ? one event counter input ? one timer output ? one input capture timer eight-bit clock-synchronous serial interface (1 channel) alarm output
hd404369 series 2 built-in oscillators ? ceramic oscillator or crystal ? external clock drive is also possible ? subclock: 32.768-khz crystal oscillator seven interrupt sources ? two by external sources ? three by timers ? one by a/d converter ? one by serial interface four low-power dissipation modes ? standby mode ? stop mode ? watch mode ? subactive mode instruction cycle time ? 0.47 m s (f osc = 8.5 mhz, 1/4 division ratio): hd40a4364, hd40a4368, hd40a43612, hd40a4369, hd407a4369 ? 0.8 m s (f osc = 5 mhz, 1/4 division ratio): hd404364, HD404368, hd4043612, hd404369 ? 1/4, 1/8, 1/16, 1/32 system clock division ratio can be selecte
hd404369 series 3 ordering information type instruction cycle time product name model name rom (words) package mask rom standard version (f osc = 5 mhz) hd404364 hd404364s 4,096 dp-64s hd404364f fp-64b hd404364h fp-64a HD404368 HD404368s 8,192 dp-64s HD404368f fp-64b HD404368h fp-64a hd4043612 hd4043612s 12,288 dp-64s hd4043612f fp-64b hd4043612h fp-64a hd404369 hd404369s 16,384 dp-64s hd404369f fp-64b hd404369h fp-64a high speed versions hd40a4364 hd40a4364s 4,096 dp-64s (f osc = 8.5 mhz) hd40a4364f fp-64b hd40a4364h fp-64a hd40a4368 hd40a4368s 8,192 dp-64s hd40a4368f fp-64b hd40a4368h fp-64a hd40a43612 hd40a43612s 12,288 dp-64s hd40a43612f fp-64b hd40a43612h fp-64a hd40a4369 hd40a4369s 16,384 dp-64s hd40a4369f fp-64b hd40a4369h fp-64a ztat ? (f osc = 8.5 mhz) hd407a4369 hd407a4369s 16,384 dp-64s hd407a4369f fp-64b hd407a4369h fp-64a
hd404369 series 4 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 fp-64b r7 2 r0 0 / sck r0 1 /si r0 2 /so r0 3 /toc test reset osc 1 osc 2 gnd x1 x2 av ss r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 r3 3 /an 3 r4 0 /an 4 r4 1 /an 5 r7 1 r7 0 r6 3 r6 2 r6 1 r6 0 ra 1 r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r4 2 /an 6 r4 3 /an 7 r5 0 /an 8 r5 1 /an 9 r5 2 /an 10 r5 3 /an 11 av cc v cc d 0 / int 0 d 1 / int 1 d 2 /evnb d 3 /buzz d 4 / stopc r1 1 r1 0 r9 3 r9 2 r9 1 r9 0 r8 3 r8 2 r8 1 r8 0 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 r1 0 r9 3 r9 2 r9 1 r9 0 r8 3 r8 2 r8 1 r8 0 d 13 d 12 d 11 d 10 d 9 d 8 d 7 r0 1 /si r0 2 /so r0 3 /toc test reset osc 1 osc 2 gnd x1 x2 av ss r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 r3 3 /an 3 r4 0 /an 4 r0 0 / sck r7 2 r7 1 r7 0 r6 3 r6 2 r6 1 r6 0 ra 1 r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r4 1 /an 5 r4 2 /an 6 r4 3 /an 7 r5 0 /an 8 r5 1 /an 9 r5 2 /an 10 r5 3 /an 11 av cc v cc d 0 / int 0 d 1 / int 1 d 2 /evnb d 3 /buzz d 4 / stopc d 5 d 6 fp-64a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 r6 0 r6 1 r6 2 r6 3 r7 0 r7 1 r7 2 r0 0 / sck r0 1 /si r0 2 /so r0 3 /toc test reset osc 1 osc 2 gnd x1 x2 av ss r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 r3 3 /an 3 r4 0 /an 4 r4 1 /an 5 r4 2 /an 6 r4 3 /an 7 r5 0 /an 8 r5 1 /an 9 r5 2 /an 10 r5 3 /an 11 av cc r8 3 r8 2 r8 1 r8 0 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 / stopc d 3 /buzz d 2 /evnb d 1 / int 1 d 0 / int 0 v cc ra 1 r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 r9 3 r9 2 r9 1 r9 0 dp-64s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52
hd404369 series 5 pin description pin number item symbol dp-64s fp-64b fp-64a i/o function power v cc 33 27 25 applies power voltage supply gnd 16 10 8 connected to ground test test 12 6 4 i cannot be used in user applications. connect this pin to gnd. reset reset 13 7 5 i resets the mcu oscillator osc 1 14 8 6 i input/output pin for the internal oscillator. connect these pins to the ceramic oscillator or crystal oscillator, or osc 1 to an external oscillator circuit. osc 2 1597o x1 17 11 9 i used with a 32.768-khz crystal ocillator for clock purposes x2 18 12 10 o port d 0 ? 13 34?7 28?1 26?9 i/o input/output pins consisting of standard voltage pins addressed individually by bits ra 1 64 58 56 i one-bit standard-voltage input port pin r0 0 ?0 3 , r3 0 ?9 3 1?1, 20?1, 48?5 1?, 14?5, 42?9, 59?4 1?, 12?3, 40?7, 57?4 i/o four-bit input/output pins consisting of standard voltage pins r1 0 ?2 3 56?3 50?7 48?5 i/o four-bit input/output pins consisting of intermediate voltage pins interrupt int 0 , int 1 34, 35 28, 29 26, 27 i input pins for external interrupts stop clear stopc 38 32 30 i input pin for transition from stop mode to active mode serial sck 8 2 64 i/o serial interface clock input/output pin interface si 9 3 1 i serial interface receive data input pin so 10 4 2 o serial interface transmit data output pin timer toc 11 5 3 o timer output pin evnb 36 30 28 i event count input pin alarm buzz 37 31 29 o square waveform output pin
hd404369 series 6 pin description (cont) pin number item symbol dp-64s fp-64b fp-64a i/o function a/d converter av cc 32 26 24 power supply for the a/d converter. connect this pin as close as possible to the v cc pin and at the same voltage as v cc . if the power supply voltage to be used for the a/d converter is not equal to v cc , connect a 0.1- m f bypass capacitor between the av cc and av ss pins. (however, this is not necessary when the av cc pin is directly connected to the v cc pin.) av ss 19 13 11 ground for the a/d converter. connect this pin as close as possible to gnd at the same voltage as gnd. an 0 ?n 11 20?1 14?5 12?3 i analog input pins for the a/d converter
hd404369 series 7 block diagram d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 r0 0 r0 1 r0 2 r0 3 d port r0 port r1 0 r1 1 r1 2 r1 3 r1 port r2 0 r2 1 r2 2 r2 3 r2 port r3 0 r3 1 r3 2 r3 3 r3 port r4 0 r4 1 r4 2 r4 3 r4 port r5 0 r5 1 r5 2 r5 3 r5 port r6 0 r6 1 r6 2 r6 3 r6 port r7 0 r7 1 r7 2 r7 port r8 0 r8 1 r8 2 r8 3 r8 port r9 0 r9 1 r9 2 r9 3 r9 port ra 1 ra port rom (16,384 10 bits) (12,288 10 bits) (4,096 10 bits) pc (14 bits) instruction decoder sp (10 bits) b (4 bits) a (4 bits) st (1 bit) ca (1 bit) alu spy (4 bits) y (4 bits) spx (4 bits) x (4 bits) w (2 bits) ram (512 4 bits) system control interrupt control timer a timer b timer c serial interface a/d converter buzzer internal data bus internal data bus internal address bus buzz av cc an 11 av ss an 0 ? ? ? ? si so sck toc evnb int 0 int 1 data bus intermediate voltage pin directional signal line gnd v cc x2 x1 osc 2 osc 1 stopc test reset (8,192 10 bits)
hd404369 series 8 memory map rom memory map the rom memory map is shown in figure 1 and described below. vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. after mcu reset or an interrupt, program execution continues from the vector address. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000-$0fff (hd404364, hd40a4364), $0000?1fff (HD404368, hd40a4368), $0000?2fff (hd4043612, hd40a43612), $0000?3fff (hd404369, hd40a4369, hd407a4369)): the entire rom area can be used for program coding. $000f $0fff $1000 $2fff $0010 $003f $0040 vector address (16 words) zero-page subroutine (64 words) program (4,096 words) program (8,192 words) $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f 0 1 jmpl instruction (jump to reset , stopc routine) jmpl instruction (jump to int routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b routine) jmpl instruction (jump to timer c routine) jmpl instruction (jump to a/d converter routine) jmpl instruction (jump to int routine) jmpl instruction (jump to serial routine) program (12,288 words) program (16,384 words) for hd404369, hd40a4369, hd407a4369 $1fff $2000 $3000 $3fff for hd404364, hd40a4364 for HD404368, hd40a4368 for hd4043612, hd40a43612 note: since the rom address areas between $0000?0fff overlap, the user can determine how these areas are to be used. figure 1 rom memory map ram memory map the mcu contains 512-digit 4 bit ram areas. these ram areas consist of a memory register area, a data area, and a stack area. in addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same ram memory space labeled as a ram-mapped register area. the ram memory map is shown in figure 2 and described below.
hd404369 series 9 ram memory map a/d channel register (acr) $000 $000 $040 $050 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $020 $023 $033 $034 $035 $036 $037 $00a $00b $00e $00f w w r/w w w w w w w w w w r r r r w r/w r/w r/w r/w r/w $3c0 ram-mapped registers memory registers (mr) stack (64 digits) interrupt control bits area port mode register a (pmra) serial mode register (smr) serial data register lower (srl) serial data register upper (sru) timer mode register a (tma) timer mode register b1 (tmb1) timer b (trbl/twbl) (trbu/twbu) miscellaneous register (mis) timer mode register c (tmc) timer c (trcl/twcl) (trcu/twcu) register flag area port r0 dcr (dcr0) port r3 dcr (dcr3) not used 1. two registers are mapped on the same area ($00a, $00b, $00e, $00f). 2. undefined. timer read register b lower (trbl) timer read register b upper (trbu) timer read register c lower (trcl) timer read register c upper (trcu) timer write register b lower (twbl) timer write register b upper (twbu) timer write register c lower (twcl) timer write register c upper (twcu) r: read only w: write only r/w: read/write $200 notes: $016 r a/d data register lower (adrl) $017 $024 $025 $026 $027 $028 $018 $019 $01a $3ff a/d data register upper (adru) a/d mode register 1 (amr1) a/d mode register 2 (amr2) r w w w port mode register b (pmrb) port mode register c (pmrc) timer mode register b2 (tmb2) system clock selection register 1 (ssr1) not used port r4 dcr (dcr4) port r5 dcr (dcr5) port r6 dcr (dcr6) port r7 dcr (dcr7) w w w w w w w w w $030 not used system clock selection register 2 (ssr2) not used not used 0000 0000 0000 undefined undefined 0000 0000 * 2 /0000 0000 0000 0000 0000 0000 1000 0000 -000 0000 00-0 -000 000- 0000 0000 0000 -000 --00 undefined * 2 /0000 undefined * 1 initial values after reset $03f data (432 digits) 0000 0000 0000 --00 port d 0 ? 3 port d 4 ? 7 port d 8 ? 11 port d 12 , d 13 port r1 dcr (dcr1) port r2 dcr (dcr2) w w 0000 0000 w w w w 0000 0000 w w port r8 dcr (dcr8) port r9 dcr (dcr9) dcr dcr dcr dcr (dcd0) (dcd1) (dcd2) (dcd3) $02c $02d $02e $02f $031 $032 $038 $039 figure 2 ram memory map
hd404369 series 10 ram-mapped register area ($000?03f): interrupt control bits area ($000?003) this area is used for interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. special function register area ($004?01f, $024?03f) this area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, a/d converter, and as data control registers for i/o ports. the structure is shown in figures 2 and 5. these registers can be classified into three types: write-only (w), read-only (r), and read/write (r/w). ram bit manipulation instructions cannot be used for these registers. register flag area ($020?023) this area is used for the dton, wdon, and other register flags and interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. memory register (mr) area ($040?04f): consisting of 16 addresses, this area (mr0?r15) can be accessed by register-register instructions (lamr and xmra). the structure is shown in figure 6. data area ($050?1ff) stack area ($3c0?3ff): used for saving the contents of the program counter (pc), status flag (st), and carry flag (ca) at subroutine call (cal or call instruction) and for interrupts. this area can be used as a 16-level nesting subroutine stack in which one level requires four digits. the data to be saved and the save conditions are shown in figure 6. the program counter is restored by either the rtn or rtni instruction, but the status and carry flags can only be restored by the rtni instruction. any unused space in this area is used for data storage.
hd404369 series 11 bit 3 bit 2 bit 1 bit 0 imta (im of timer a) ifta (if of timer a) im1 (im of int 1 ) if1 (if of int 1 ) imtc (im of timer c) iftc (if of timer c) imtb (im of timer b) iftb (if of timer b) ims (im of serial) ifs (if of serial) imad (im of a/d) ifad (if of a/d) $000 $001 $002 $003 interrupt control bits area im0 (im of int 0 ) if0 (if of int 0 ) rsp (reset sp bit) ie (interrupt enable flag) icsf (input capture status flag) $020 $021 $022 $023 register flag area dton (direct transfer on flag) adsf (a/d start flag) wdon (watchdog on flag) lson (low speed on flag) icef (input capture error flag) rame (ram enable flag) iaof (i ad off flag) if: im: ie: sp: interrupt request flag interrupt mask interrupt enable flag stack pointer bit 3 bit 2 bit 1 bit 0 not used figure 3 configuration of interrupt control bits and register flag areas ie im lson iaof if icsf icef rame rsp wdon adsf not used dton sem/semd rem/remd tm/tmd allowed allowed allowed not executed allowed allowed not executed allowed inhibited allowed not executed inhibited allowed inhibited allowed not executed in active mode allowed allowed used in subactive mode not executed not executed inhibited note: wdon is reset by mcu reset or by stopc enable for stop mode cancellation. the rem or remd instuction must not be executed for adsf during a/d conversion. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 4 usage limitations of ram bit manipulation instructions
hd404369 series 12 $000 $003 pmra $004 smr $005 srl $006 sru $007 tma $008 tmb1 $009 trbl/twbl $00a trbu/twbu $00b mis $00c tmc $00d trcl/twcl $00e trcu/twcu $00f acr $016 adrl $017 adru $018 amr1$019 amr2 $01a $020 $023 pmrb $024 pmrc $025 tmb2 $026 ssr1 $027 ssr2 $028 dcd0 $02c dcd1 $02d dcd2 $02e dcd3 $02f dcr0 $030 dcr1 $031 dcr2 $032 dcr3 $033 dcr4 $034 dcr5 $035 dcr6 $036 dcr7 $037 dcr8 $038 dcr9 $039 $03f bit 3 bit 2 bit 1 interrupt control bits area d 3 /buzz r0 3 /toc r0 2 /so serial transmit clock speed selection serial data register (lower digit) serial data register (upper digit) clock source selection (timer a) clock source selection (timer b) timer b register (lower digit) timer b register (upper digit) so pmos control interrupt frame period selection clock source selection (timer c) timer c register (lower digit) timer c register (upper digit) analog channel selection a/d data register (lower digit) a/d data register (upper digit) register flag area port d 3 dcd port d 7 dcd port d 2 dcd port d 6 dcd port d 1 dcd port d 5 dcd port d 9 dcd port d 0 dcd port d 4 dcd port d 8 dcd port r0 3 dcr port r2 3 dcr port d 11 dcd port r4 3 dcr port r5 3 dcr port r6 3 dcr port r0 2 dcr port r2 2 dcr port d 10 dcd port r4 2 dcr port r5 2 dcr port r6 2 dcr port r7 2 dcr port r0 1 dcr port r1 1 dcr port r2 1 dcr port d 13 dcd port r4 1 dcr port r5 1 dcr port r6 1 dcr port r7 1 dcr port r0 0 dcr port r1 0 dcr port r2 0 dcr port d 12 dcd port r4 0 dcr port r5 0 dcr port r6 0 dcr port r7 0 dcr 1. 2. 3. 4. 5. 6. 7. 8. 9. r0 0 / sck bit 0 1 * 2 * 3 * 2 * timer-a/time-base auto-reload on/off pull-up mos control a/d conversion time so output level control in idle states serial clock source selection input capture selection 32-khz oscillation stop 32-khz oscillation division ratio notes: r0 1 /si not used r3 3 /an 3 r3 2 /an 2 r3 1 /an 1 r3 0 /an 0 4 * r5/an 8 ?n 11 r4/an 4 ?n 7 port r8 3 dcr port r9 3 dcr port r8 2 dcr port r9 2 dcr port r8 1 dcr port r9 1 dcr port r8 0 dcr port r9 0 dcr d 4 / stopc buzzer output * 8 d 2 /evnb * 7 * 9 d 1 / int 1 * 5 evnb detection edge selection clock select d 0 / int 0 * 6 not used clock division ratio selection port r1 3 dcr port r3 3 dcr port r1 2 dcr port r3 2 dcr port r3 1 dcr port r3 0 dcr not used not used not used not used not used not used not used not used figure 5 special function register area
hd404369 series 13 memory registers $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f mr(0) mr(1) mr(2) mr(3) mr(4) mr(5) mr(6) mr(7) mr(8) mr(9) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 mr(10) mr(11) mr(12) mr(13) mr(14) mr(15) pc pc pc pc pc pc pc pc pc pc pc pc st pc ca pc 10 3 13 9 6 2 12 8 5 1 11 7 4 0 bit 3 bit 2 bit 1 bit 0 pc ?c : st: status flag ca: carry flag program counter 13 stack area 0 $3c0 $3ff $3fc $3fd $3fe $3ff figure 6 configuration of memory registers and stack area, and stack position
hd404369 series 14 functional description registers and flags the mcu has nine registers and two flags for cpu operations. they are shown in figure 7 and described below. 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 7 registers and flags accumulator (a), b register (b): four-bit registers used to hold the results from the arithmetic logic unit (alu) and transfer data between memory, i/o, and other registers. w register (w), x register (x), y register (y): two-bit (w) and four-bit (x and y) registers used for indirect ram addressing. the y register is also used for d-port addressing.
hd404369 series 15 spx register (spx), spy register (spy): four-bit registers used to supplement the x and y registers. carry flag (ca): one-bit flag that stores any alu overflow generated by an arithmetic operation. ca is affected by the sec, rec, rotl, and rotr instructions. a carry is pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. status flag (st): one-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the alu, or result of a bit test. st is used as a branch condition of the br, brl, cal, and call instructions. the contents of st remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the br, brl, cal, or call instruction is read, regardless of whether the instruction is executed or skipped. the contents of st are pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. program counter (pc): 14-bit binary counter that points to the rom address of the instruction being executed. stack pointer (sp): ten-bit pointer that contains the address of the stack area to be used next. the sp is initialized to $3ff by mcu reset. it is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. the top four bits of the sp are fixed at 1111, so a stack can be used up to 16 levels. the sp can be initialized to $3ff in another way: by resetting the rsp bit with the rem or remd instruction. reset the mcu is reset by inputting a low-level voltage to the reset pin. at power-on or when stop mode is cancelled, reset must be low for at least one t rc to enable the oscillator to stabilize. during operation, reset must be low for at least two instruction cycles. initial values after mcu reset are listed in table 1. interrupts the mcu has 7 interrupt sources: two external signals ( int 0 and int 1 ), three timer/counters (timers a, b, and c), serial interface, and a/d converter. an interrupt request flag (if), interrupt mask (im), and vector address are provided for each interrupt source, and an interrupt enable flag (ie) controls the entire interrupt process. interrupt control bits and interrupt processing: locations $000 to $003 in ram are reserved for the interrupt control bits which can be accessed by ram bit manipulation instructions. the interrupt request flag (if) cannot be set by software. mcu reset initializes the interrupt enable flag (ie) and the if to 0 and the interrupt mask (im) to 1. a block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in table 3.
hd404369 series 16 an interrupt request occurs when the if is set to 1 and the im is set to 0. if the ie is 1 at that point, the interrupt is processed. a priority programmable logic array (pla) generates the vector address assigned to that interrupt source. the interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in figure 10. after an interrupt is acknowledged, the previous instruction is completed in the first cycle. the ie is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. program the jmpl instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the if by a software instruction within the interrupt program.
hd404369 series 17 table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 interrupt flags/mask interrupt enable flag (ie) 0 inhibits all interrupts interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt requests i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcd0- dcd2) all bits 0 turns output buffer off (to high impedance) (dcd3) - - 00 (dcr0 dcr6, dcr8, dcr9) all bits 0 (dcr7) - 000 port mode register a (pmra) 0000 refer to description of port mode register a port mode register b bits 2? (pmrb2 pmrb0) 000 refer to description of port mode register b port mode register c (pmrc) 00 - 0 refer to description of port mode register c timer/count- ers, serial interface timer mode register a (tma) 0000 refer to description of timer mode register a timer mode register b1 (tmb1) 0000 refer to description of timer mode register b1 timer mode register b2 (tmb2) - 000 refer to description of timer mode register b2 timer mode register c (tmc) 0000 refer to description of timer mode register c serial mode register (smr) 0000 refer to description of serial mode register prescaler s (pss) $000 prescaler w (psw) $00 timer counter a (tca) $00 timer counter b (tcb) $00 timer counter c (tcc) $00 timer write register b (twbu, twbl) $x0 timer write register c (twcu, twcl) $x0 octal counter 000
hd404369 series 18 item abbr. initial value contents a/d a/d mode register 1 (amr1) 0000 refer to description of a/d mode register a/d mode register 2 (amr2) - 000 a/d channel register (acr) 0000 refer to description of a/d channel register a/d data register (adrl) 0000 refer to description of a/d data register (adru) 1000 bit registers low speed on flag (lson) 0 refer to description of operati ng mod es watchdog timer on flag (wdon) 0 refer to description of timer c a/d start flag (adsf) 0 refer to description of a/d converter i ad off flag (iaof) 0 refer to the description of a/d converter direct transfer on flag (dton) 0 refer to description of operati ng mod es input capture status flag (icsf) 0 refer to description of timer b input capture error flag (icef) 0 refer to description of timer b others miscellaneous register (mis) 0000 refer to description of operati ng modes, i/o, and serial interface system clock select register 1 (ssr1) 000 - refer to description of operati ng modes, and oscillation circuits system clock select register 2 (ssr2) - - 00 refer to description of oscillation circuits notes: 1. the statuses of other registers and flags after mcu reset are shown in the following table. 2. x indicates invalid value. ?indicates that the bit does not exist.
hd404369 series 19 item abbr. status after cancellation of stop mode by stopc input status after all other types of reset carry flag (ca) pre-stop-mode values are not guaranteed; values must be initialized by program pre-mcu-reset values are not guaranteed; values must be initialized by program accumulator (a) b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) serial data register (srl, sru) ram pre-stop-mode values are retained ram enable flag (rame) 1 0 port mode register b bit 3 (pmrb3) pre-stop-mode values are retained 0 system clock select register 1 bit 3 (ssr13) table 2 vector addresses and interrupt priorities reset/interrupt priority vector address reset , stopc * $0000 int 0 1 $0002 int 1 2 $0004 timer a 3 $0006 timer b 4 $0008 timer c 5 $000a a/d 6 $000c serial 7 $000e note: * the stopc interrupt request is valid only in stop mode.
hd404369 series 20 ie ifo imo if1 im1 ifta imta iftb imtb iftc imtc ifad imad $ 000,0 $ 000,2 $ 000,3 $ 001,0 $ 001,1 $ 001,2 $ 001,3 $ 002,0 $ 002,1 $ 002,2 $ 002,3 $ 003,0 $ 003,1 sequence control ?push pc/ca/st ?reset ie ?jump to vector address priority control logic vector address note: $m,n is ram address $m, bit number n. ifs ims $ 003,2 $ 003,3 int 0 interrupt int 1 interrupt timer a interrupt timer b interrupt timer c interrupt a/d interrupt serial interrupt figure 8 interrupt control circuit
hd404369 series 21 table 3 interrupt processing and activation conditions interrupt source int 0 int 1 timer a timer b timer c a/d serial ie 1111111 if0 im0 1000000 if1 im1 * 100000 ifta imta ** 10000 iftb imtb ** * 10 00 iftc imtc **** 100 ifad imad ***** 10 ifs ims ****** 1 note: bits marked * can be either 0 or 1. their values have no effect on operation. instruction cycles 123456 instruction execution * ie reset interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine vector address generation note: * the stack is accessed and the ie reset after the instruction is executed, even if it is a two-cycle instruction. stacking figure 9 interrupt processing sequence
hd404369 series 22 power on reset = 0? reset mcu interrupt request? execute instruction pc (pc) + 1 ? pc $0002 ? pc $0004 ? pc $0006 ? pc $0008 ? pc $000a ? pc $000e ? ie = 1? accept interrupt ie 0 stack (pc) stack (ca) stack (st) ? int 0 interrupt? int 1 interrupt? timer-a interrupt? timer-b interrupt? no yes no yes no yes yes yes yes yes yes no no no no ? ? ? (serial interrupt) pc $000c ? a/d interrupt? yes no no timer-c interrupt? figure 10 interrupt processing flowchart
hd404369 series 23 interrupt enable flag (ie: $000, bit 0): controls the entire interrupt process. it is reset by the interrupt processing and set by the rtni instruction, as listed in table 4. table 4 interrupt enable flag (ie: $000, bit 0) ie interrupt enabled/disabled 0 disabled 1 enabled external interrupts ( int 0 , int 1 ): two external interrupt signals. external interrupt request flags (if0: $000, bit 2; if1: $001, bit 0): if0 and if1 are set at the rising edge of signals input to int 0 and int 1 , as listed in table 5. table 5 external interrupt request flags (if0: $000, bit2; if1: $001, bit 0) if0, if1 interrupt request 0no 1 yes external interrupt masks (im0: $000, bit 3; im1: $001, bit 1): prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. table 6 external interrupt masks (im0: $000, bit 3; im1: $001, bit 1) im0, im1 interrupt request 0 enabled 1 disabled (masked) timer a interrupt request flag (ifta: $001, bit 2): set by overflow output from timer a, as listed in table 7. table 7 timer a interrupt request flag (ifta: $001, bit 2) ifta interrupt request 0no 1 yes timer a interrupt mask (imta: $001, bit 3): prevents (masks) an interrupt request caused by the timer a interrupt request flag, as listed in table 8.
hd404369 series 24 table 8 timer a interrupt mask (imta: 001, bit 3) imta interrupt request 0 enabled 1 disabled (masked) timer b interrupt request flag (iftb: $002, bit 0): set by overflow output from timer b, as listed in table 9. table 9 timer b interrupt request flag (iftb: $002, bit 0) iftb interrupt request 0no 1 yes timer b interrupt mask (imtb: $002, bit 1): prevents (masks) an interrupt request caused by the timer b interrupt request flag, as listed in table 10. table 10 timer b interrupt mask (imtb: $002, bit 1) imtb interrupt request 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): set by overflow output from timer c, as listed in table 11. table 11 timer c interrupt request flag (iftc: $002, bit 2) iftc interrupt request 0no 1 yes timer c interrupt mask (imtc: $002, bit 3): prevents (masks) an interrupt request caused by the timer c interrupt request flag, as listed in table 12. table 12 timer c interrupt mask (imtc: $002, bit 3) imtc interrupt request 0 enabled 1 disabled (masked)
hd404369 series 25 serial interrupt request flag (ifs: $003, bit 2): set when data transfer is completed or when data transfer is suspended, as listed in table 13. table 13 serial interrupt request flag (ifs: $003, bit 2) ifs interrupt request 0no 1 yes serial interrupt mask (ims: $003, bit 3): prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 14. table 14 serial interrupt mask (ims: $003, bit 3) mask ims interrupt request 0 enabled 1 disabled (masked) a/d interrupt request flag (ifad: $003, bit 0): set at the completion of a/d conversion, as listed in table 15. table 15 a/d interrupt request flag (ifad: $003, bit 0) ifad interrupt request 0no 1 yes a/d interrupt mask (imad: $003, bit 1): prevents (masks) an interrupt request caused by the a/d interrupt request flag, as listed in table 16. table 16 a/d interrupt mask (imad: $003, bit 1) imad interrupt request 0 enabled 1 disabled (masked)
hd404369 series 26 operating modes the mcu has five operating modes as shown in table 17. the operations in each mode are listed in tables 18 and 19. transitions between operating modes are shown in figure 11. active mode: all mcu functions operate according to the clock generated by the system oscillator osc 1 and osc 2 . table 17 operating modes and clock status mode name active standby stop watch subactive * 2 activation method reset cancellation, interrupt stopc cancellation in stop mode, stop/sby instruction in subactive mode (when direct transfer is selected) sby instruction stop instruction when tma3 = 0 stop instruction when tma3 = 1 int 0 or timer a interrupt request from watch mode status system oscillator op op stopped stopped stopped subsystem oscillator op op * 1 op op op cancellation method reset input, stop/sby instruction reset input, interrupt request reset input, stopc input in stop mode reset input, int 0 or timer a interrupt request reset input, stop/sby instruction notes: op implies in operation 1. operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register 1 (ssr1: $027). 2. subactive mode is an optional function; specify it on the function option list.
hd404369 series 27 table 18 operations in low-power dissipation modes function stop mode watch mode standby mode subactive mode cpu reset retained retained op ram retained retained retained op timer a reset op op op timer b reset stopped op op timer c reset stopped op op serial reset stopped op op a/d reset stopped op stopped i/o reset retained retained op note: op implies in operation table 19 i/o status in low-power dissipation modes output input standby mode, watch mode stop mode active mode, subactive mode ra 1 input enabled d 0 ? 13 , r0?9 retained or output of peripheral functions high impedance input enabled
hd404369 series 28 reset by reset input or by watchdog timer f osc : f x : cpu : clk : per : oscillate oscillate stop f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate stop f w f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f w f cyc f osc : f x : cpu : clk : per : stop oscillate f sub f w f sub f osc : f x : cpu : clk : per : stop stop stop stop stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop standby mode stop mode (tma3 = 0, ssr13 = 1) watch mode subactive mode (tma3 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) sby interrupt sby interrupt stop int 0 , timer a * stop 1. interrupt source 2. stop/sby (dton = 1, lson = 0) 3. stop/sby (dton = 0, lson = 0) 4. stop/sby (dton = don? care, lson = 1) f osc : f x : f cyc : f sub : f w : lson: dton: main oscillation frequency suboscillation frequency for time-base f osc /4, f osc /8, f osc /16, f osc /32 f x /8 or f x /4 (software selectable) f x /8 system clock clock for time-base clock for other peripheral functions low speed on flag direct transfer on flag active mode notes: cpu : clk : per : f osc : f x : cpu : clk : per : stop oscillate stop stop stop (tma3 = 0, ssr13 = 0) reset1 reset2 rame = 0 rame = 1 int 0 , timer a (tma3 = 0) stop stopc stopc stop 1 * 2 * 3 * 1 * 4 (software selectable) f figure 11 mcu status transitions
hd404369 series 29 standby mode: in standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. therefore, the cpu operation stops, but all ram and register contents are retained, and the d or r port status, when set to output, is maintained. peripheral functions such as interrupts, timers, and serial interface continue to operate. the power dissipation in this mode is lower than in active mode because the cpu stops. the mcu enters standby mode when the sby instruction is executed in active mode. standby mode is terminated by a reset input or an interrupt request. if it is terminated by reset input, the mcu is reset as well. after an interrupt request, the mcu enters active mode and executes the next instruction after the sby instruction. if the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. a flowchart of operation in standby mode is shown in figure 12.
hd404369 series 30 standby oscillator: active peripheral clocks: active all other clocks: stop no yes no yes no yes no yes no yes no yes yes (sby only) watch oscillator: stop suboscillator: active peripheral clocks: stop all other clocks: stop restart processor clocks reset mcu execute next instruction accept interrupt restart processor clocks no yes if = 1, im = 0, and ie = 1? reset = 0? if0 ? im0 = 1? if1 ? im1 = 1? ifta ? imta = 1? iftb ? imtb = 1? iftc ? imtc = 1? ifad ? imad = 1? no yes ifs ? ims = 1? no stop oscillator: stop suboscillator: active/stop peripheral clocks: stop all other clocks: stop reset = 0? stopc = 0? rame = 1 rame = 0 yes yes no no execute next instruction (sby only) (sby only) (sby only) (sby only) figure 12 mcu operation flowchart stop mode: in stop mode, all mcu operations stop and ram data is retained. therefore, the power dissipation in this mode is the least of all modes. the osc 1 and osc 2 oscillator stops. for the x1 and x2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register 1 (ssr1: $027; operating: ssr13 = 0, stop: ssr13 = 1) (figure 23). the mcu enters stop mode if the stop instruction is executed in active mode when bit 3 of timer mode register a (tma: $008) is set to 0 (tma3 = 0) (figure 37). stop mode is terminated by a reset input or a stopc input as shown in figure 13. reset or stopc must be applied for at least one t rc to stabilize oscillation (refer to the ac characteristics section). when the mcu restarts after stop mode is cancelled, all ram contents before entering stop mode are retained,
hd404369 series 31 but the accuracy of the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and serial data register cannot be guaranteed. watch mode: in watch mode, the clock function (timer a) using the x1 and x2 oscillator operates, but other function operations stop. therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. in this mode, the osc 1 and osc 2 oscillator stops, but the x1 and x2 oscillator operates. the mcu enters watch mode if the stop instruction is executed in active mode when tma3 = 1, or if the stop or sby instruction is executed in subactive mode. watch mode is terminated by a reset input or a timer-a/ int 0 interrupt request. for details of reset input, refer to the stop mode section. when terminated by a timer-a/ int 0 interrupt request, the mcu enters active mode if lson = 0, or subactive mode if lson = 1. after an interrupt request is generated, the time required to enter active mode is t rc for a timer a interrupt, and t x (where t + t rc < t x < 2t + t rc ) for an int 0 interrupt, as shown in figures 14 and 15. operation during mode transition is the same as that at standby mode cancellation (figure 12). stop mode oscillator internal clock stop instruction execution t res 3 t rc (stabilization period) t res reset or stopc figure 13 timing of stop mode cancellation subactive mode: the osc 1 and osc 2 oscillator stops and the mcu operates with a clock generated by the x1 and x2 oscillator. in this mode, functions except the a/d conversion operate. however, because the operating clock is slow, the power dissipation becomes low, next to watch mode. the cpu instruction execution speed can be selected as 244 m s or 122 m s by setting bit 2 (ssr12) of the system clock select register 1 (ssr1: $027). note that the ssr12 value must be changed in active mode. if the value is changed in subactive mode, the mcu may malfunction. when the stop or sby instruction is executed in subactive mode, the mcu enters either watch or active mode, depending on the statuses of the low speed on flag (lson: $020, bit 0) and the direct transfer on flag (dton: $020, bit 3). interrupt frame: in watch and subactive modes, clk is applied to timer a and the int 0 circuit. prescaler w and timer a operate as the time-base and generate the timing clock for the interrupt frame. three interrupt frame lengths (t) can be selected by setting the miscellaneous register (mis: $00c) (figure 15). in watch and subactive modes, the timer-a/ int 0 interrupt is generated synchronously with the interrupt frame. the interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. the falling edge of the int 0 signal is input asynchronously with the interrupt
hd404369 series 32 frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. an overflow and interrupt request in timer a is generated synchronously with the interrupt strobe timing. t rc t t x t t: t : interrupt frame length oscillation stabilization period rc (during the transition from watch mode to active mode only) interrupt strobe int 0 interrupt request generation active mode watch mode active mode oscillation stabilization period t + t rc t x 2t + t rc figure 14 interrupt frame direct transition from subactive mode to active mode: available by controlling the direct transfer on flag (dton: $020, bit 3) and the low speed on flag (lson: $020, bit 0). the procedures are described below: set lson to 0 and dton to 1 in subactive mode. execute the stop or sby instruction. the mcu automatically enters active mode from subactive mode after waiting for the mcu internal processing time and oscillation stabilization time (figure 16). notes: 1. the dton flag ($020, bit 3) can be set only in subactive mode. it is always reset in active mode. 2. the transition time (t d ) from subactive mode to active mode: t rc < t d < t + t rc
hd404369 series 33 bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 mis0 t * 0 0.24414 ms t rc 0.12207 ms 0.24414 ms 7.8125 ms 62.5 ms oscillation circuit conditions external clock input ceramic oscillator 0 1 1 1 0 1 15.625 ms 125 ms not used notes: 1. 2. the values of t and t rc are applied when a 32.768-khz crystal oscillator is used. the value is applied only when direct transfer operation is used. buffer control. refer to figure 34. mis3 mis2 1 * 1 * 2 crystal oscillator figure 15 miscellaneous register (mis) subactive mode interrupt strobe direct transfer completion timing mcu internal processing period oscillation stabilization time active mode t t rc t: t rc : t d : stop/sby instruction execution (set lson = 0, dton = 1) interrupt frame length oscillation stabilization period transition time t d figure 16 direct transition timing stop mode cancellation by stopc : the mcu enters active mode from stop mode by inputting stopc as well as by r e se t . in either case, the mcu starts instruction execution from the starting address (address 0) of the program. however, the value of the ram enable flag (rame: $021, bit 3) differs between cancellation by stopc and by r e se t . when stop mode is cancelled by r eset , rame = 0; when cancelled by stopc , rame = 1. reset can cancel all modes, but stopc is valid only in stop mode; stopc input is ignored in other modes. therefore, when the program requires to confirm that stop mode has been cancelled by stopc (for example, when the ram contents before entering stop mode is
hd404369 series 34 used after transition to active mode), execute the test instruction to the ram enable flag (rame) at the beginning of the program. mcu operation sequence: the mcu operates in the sequence shown in figures 17 to 19. it is reset by an asynchronous reset input, regardless of its status. the low-power mode operation sequence is shown in figure 19. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sbyinstruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset = 0 ? rame = 0 reset mcu mcu operation cycle no yes figure 17 mcu operating sequence (power on)
hd404369 series 35 mcu operation cycle if = 1? instruction execution sby/stop instruction? pc next location pc vector address low-power mode operation cycle ie 0 stack (pc), (ca), (st) im = 0 and ie = 1? ? ? ? yes no no yes yes no if: im: ie: pc: ca: st: ? interrupt request flag interrupt mask interrupt enable flag program counter carry flag status flag figure 18 mcu operating sequence (mcu operation cycle)
hd404369 series 36 low-power mode operation cycle if = 1 and im = 0? hardware nop execution ? pc next iocation mcu operation cycle standby/watch mode if = 1 and im = 0? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes for if and im operation, refer to figure 12. stopc = 0? rame = 1 reset mcu no yes figure 19 mcu operating sequence (low-power mode operation) note: when the mcu is in watch mode or subactive mode, if the high level period before the falling edge of int 0 is shorter than the interrupt frame, int 0 is not detected. also, if the low level period after the falling edge of int 0 is shorter than the interrupt frame, int 0 is not detected. edge detection is shown in figure 20. the level of the int 0 signal is sampled by a sampling clock. when this sampled value changes to low from high, a falling edge is detected. in figure 21, the level of the int 0 signal is sampled by an interrupt frame. in (a) the sampled value is low at point a, and also low at point b. therefore, a falling edge is not detected. in (b), the sampled value is high at point a, and also high at point b. a falling edge is not detected in this case either. when the mcu is in watch mode or subactive mode, keep the high level and low level period of int 0 longer than the interrupt frame
hd404369 series 37 high low int sampling 0 low figure 20 edge detection a: low b: low int interrupt frame 0 a: high b: high int interrupt frame 0 (a) high level period (b) low level period figure 21 sampling example
hd404369 series 38 oscillator circuit a block diagram of the clock generation circuit is shown in figure 22. as shown in table 20, a ceramic oscillator or crystal oscillator can be connected to osc 1 and osc 2 , and a 32.768-khz oscillator can be connected to x1 and x2. the system oscillator can also be operated by an external clock. registers for oscillator circuit operation system clock selection register 1 (ssr1: $027): four bit write-only register which sets the subsystem clock frequency (f sub ) division ratio, and sets the subsystem clock oscillation in stop mode. bit 1 (ssr11) of system clock select register 1 must be set according to the frequency of the oscillator connected to osc 1 and osc 2 (figure 23). bit 1 (ssr11) and bit 2 (ssr12) are initialized to 0 on reset and in stop mode. bit 3 (ssr13) is initialized to 0 only on reset. osc 2 osc 1 x1 x2 system oscillator sub- system oscillator 1/4, 1/8, 1/16 or 1/32 division circuit * 1 timing generator circuit system clock selection cpu with rom, ram, registers, flags, and i/o peripheral function interrupt time-base interrupt time-base clock selection 1/8 or 1/4 division circuit * 2 timing generator circuit timing generator circuit 1/8 division circuit f w f sub t subcyc lson tma3 f cyc t cyc f osc f x t wcyc cpu per clk notes: 1/4, 1/8, 1/16 or 1/32 division ratio can be selected by setting bits 0 and 1 of system clock select register 2 (ssr2: $028). 1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1 (ssr1: $027). 1. 2. figure 22 clock generation circuit
hd404369 series 39 bit initial value read/write bit name 3 0 w ssr13 * 1 2 0 w ssr12 0 ? ? not used 1 0 w ssr11 system clock selection register 1 (ssr1: $027) system clock selection 0.4 to 1.0 mhz 1.6 to 5.0 mhz (hd404369 series) 1.6 to 8.5 mhz (hd40a4369 series) ssr11 0 1 ssr12 0 1 ratio selection f sub = f x /8 f sub = f x /4 32-khz oscillation division ssr13 0 1 32-khz oscillation stop oscillation operates in stop mode oscillation stops in stop mode * 2 notes: 1. ssr13 will only be cleared to 0 by a reset input. a stopc input during stop mode will not clear ssr13. also note that ssr13 will not be cleared upon transition to stop mode. 2. if f osc = 0.4 to 1.0 mhz, ssr11 must be set 0; if f osc = 1.6 to 8.5 mhz, ssr11 must be set to 1. do not use f osc = 1.0 to 1.6 mhz with 32-khz oscillation. figure 23 system clock selection register 1 (ssr1) system clock selection register 2 (ssr2: $028): four bit write-only register which is used to select the system clock divisor (figure 24). the division ratio of the system clock can be selected as 1/4, 1/8, 1/16, or 1/32 by setting bits 0 and 1 (ssr20, ssr21) of system clock select register 2 (ssr2). the values of ssr20 and ssr21 are valid after the mcu enters watch mode. the system clock must be stopped when the division ratio is to be changed. there are two methods for changing the system clock divisor, as follows. in active mode, set the divisor by writing to ssr20 and ssr21. at this point, the prior divisor setting will remain in effect. now, switch to watch mode, and then return to active mode. when active mode resumes, the system clock divisor will have switched to the new value. in subactive mode, set the divisor by writing to ssr20 and ssr21. then return to active mode through watch mode. when active mode resumes, the system clock divisor will have switched to the new value. (the change will also take effect for direct transition to active mode.)
hd404369 series 40 ssr2 is initialized to $0 on reset or in stop mode. notes on usage if the system clock select register 1 (ssr1: $027) setting does not match the oscillator frequency, the subsystem using the 32.768-khz oscillation will malfunction. bit initial value read/write bit name 3 ? ? not used 2 ? ? not used 0 0 w ssr20 1 0 w ssr21 system clock selection register 2 (ssr2: $028) ssr21 0 0 1 1 ssr20 0 1 0 1 system clock division ratio 1/4 division 1/8 division 1/16 division 1/32 division figure 24 system clock selection register 2 (ssr2)
hd404369 series 41 table 20 oscillator circuit examples circut configuration circut constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic gnd ceramic oscillator: csa4.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% crystal oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f crystal gnd l s c r s c 0 osc 1 osc 2 r f = 1 m w 20% c 1 = c 2 = 10 to 22 pf 20% crystal: equivalent to circuit shown below c 0 = 7 pf max. r s = 100 w max. crystal oscillator (x1, x2) x1 c 1 2 c x2 crystal gnd l s c r s c 0 x1 x2 crystal: 32.768 khz: mx38t (nippon denpa) c 1 = c 2 = 20 pf 20% r s = 14 k w c 0 = 1.5 pf notes: 1. since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. wiring among osc 1 , osc 2 , x1, x2 and elements should be as short as possible, and must not cross other wiring (see figure 25). 3. when a 32.768-khz crystal oscillator is not used, fix pin x1 to gnd and leave pin x2 open.
hd404369 series 42 reset osc 1 osc 2 gnd x1 x2 av ss gnd figure 25 typical layout of crystal and ceramic oscillators
hd404369 series 43 input/output the mcu has 53 input/output pins (d 0 ? 13 , r0?9) and an input pin (ra 1 ). the features are described below. eight pins (r1?2) are high-current (15 ma max) input/output with intermediate voltage nmos open drain pins. the d 0 ? 4 , r0, r3?5 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. for these pins, the peripheral function setting is done prior to the d or r port setting. therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. peripheral function output pins are cmos output pins. only the r0 2 /so pin can be set to nmos open- drain output by software. in stop mode, the mcu is reset, and therefore peripheral function selection is cancelled. input/output pins are in high-impedance state. each input/output pin except for r1 and r2 has a built-in pull-up mos, which can be individually turned on or off by software. i/o buffer configuration is shown in figure 26, programmable i/o circuits are listed in table 21, and i/o pin circuit types are shown in table 22.
hd404369 series 44 table 21 programmable i/o circuits mis3 (bit 3 of mis) 0 1 dcd, dcr 0 1 0 1 pdr 0101 010 1 cmos buffer pmos ?n on nmos on on pull-up mos ?n on note: ?indicates off status. mis3 input control signal v cc pull-up mos dcd, dcr pdr input data v cc hlt pull-up control signal buffer control signal output data figure 26 i/o buffer configuration
hd404369 series 45 table 22 circuit configuration of i/o pins i/o pin type circuit pins input/output pins v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 pdr input control signal dcd, dcr d 0 ? 13 , r0 0 , r0 1 , r0 3 r3 0 ?9 3 v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcr pdr input control signal mis2 r0 2 hlt dcr pdr input data output data input control signal r1 0 ?2 3 input pins input data input control signal ra 1 notes on next page.
hd404369 series 46 i/o pin type circuit pins peripheral function pins input/output pins v cc v cc pull-up control signal output data input data hlt mis3 sck sck sck output pins v cc v cc pull-up control signal pmos control signal output data hlt mis3 so mis2 so v cc v cc pull-up control signal output data hlt mis3 toc, buzz toc, buzz input pins input data v cc hlt mis3 si, int 0 , int 1 , evnb, stopc pdr si, int 0 , int 1 , evnb, stopc v cc hlt mis3 a/d input pdr input control signal an 0 ?n 11 notes: 1. in stop mode, the mcu is reset and the peripheral function selection is cancelled. the hlt signal goes low, and input/output pins enter the high-impedance state. 2. the hlt signal is 1 in active, standby, watch, and subactive modes.
hd404369 series 47 evaluation chip set and ztat ? /mask rom product differences as shown in figure 27, the nmos intermediate-voltage open drain pin circuit in the evaluation chip set differs from that used in the ztat ? microcomputer and built-in mask rom microcomputer products. please note that although these outputs in the ztat ? microcomputer and built-in mask rom microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs cannot be set to high impedance in the evaluation chip set. table 23 program control of high impedance states register set value dcr 0 1 pdr * 1 notes: * an asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation. this applies to the ztat ? and built-in mask rom microcomputer nmos open drain pins. v cc v cc hlt mis3 dcr pdr cpu input input control signal (a) evaluation chip set circuit structure input control signal (b) ztat and built-in mask rom microcomputer circuit structure hlt dcr pdr cpu input ? figure 27 nmos intermediate-voltage open drain pin circuits
hd404369 series 48 d port (d 0 ? 13 ): consist of 14 input/output pins addressed by one bit. pins d 0 ? 13 are set by the sed and sedd instructions, and reset by the red and redd instructions. output data is stored in the port data register (pdr) for each pin. all pins d 0 ? 13 are tested by the td and tdd instructions. the on/off statuses of the output buffers are controlled by d-port data control registers (dcd0?cd3: $02c?02f) that are mapped to memory addresses (figure 28). pins d 0 ? 2 , d 4 are multiplexed with peripheral function pins int 0 , int 1 , evnb, and stopc , respectively. the peripheral function modes of these pins are selected by bits 0? (pmrb0?pmrb3) of port mode register b (pmrb: $024) (figure 29). pin d 3 is multiplexed with peripheral function pin buzz. the peripheral function mode of this pin is selected by bit 3 (pmra3) of port mode register a (pmra: $004) (figure 30). r ports (r0 0 ?9 3 ): 39 input/output pins addressed in 4-bit units. data is input to these ports by the lar and lbr instructions, and output from them by the lra and lrb instructions. output data is stored in the port data register (pdr) for each pin. the on/off statuses of the output buffers of the r ports are controlled by r-port data control registers (dcr0?cr9: $030?039) that are mapped to memory addresses (figure 28). pin r0 0 is multiplexed with peripheral function pin sck . the peripheral function mode of this pin is selected by bit 3 (smr3) of serial mode register (smr: $005) (figure 31). pins r0 1 ?0 3 are multiplexed with peripheral pins si, so and toc, respectively. the peripheral function modes of these pins are selected by bits 0? (pmra0?mra2) of port mode register a (pmra: $004), as shown in figure 30. port r3 is multiplexed with peripheral function pins an 0 ?n 3 , respectively. the peripheral function modes of these pins can be selected by individual pins, by setting a/d mode register 1 (amr1: $019) (figure 32). ports r4 and r5 are multiplexed with peripheral function pins an 4 ?n 11 , respectively. the peripheral function modes of these pins can be selected in 4-pin units by setting bits 1 and 2 (amr21, amr22) of a/d mode register 2 (amr2: $01a) (figure 33). pull-up mos transistor control: a program-controlled pull-up mos transistor is provided for each input/output pin. the on/off status of all these transistors is controlled by bit 3 (mis3) of the miscellaneous register (mis: $00c), and the on/off status of an individual transistor can also be controlled by the port data register (pdr) of the corresponding pin?nabling on/off control of that pin alone (table 21 and figure 34). the on/off status of each transistor and the peripheral function mode of each pin can be set independently. how to deal with unused i/o pins: i/o pins that are not needed by the user system (floating) must be connected to v cc to prevent lsi malfunctions due to noise. these pins must either be pulled up to v cc by their pull-up mos transistors or by resistors of about 100 k w .
hd404369 series 49 bit initial value read/write bit name 3 0 w 2 0 w 0 0 w 1 0 w dcd0 to dcd3, dcr0 to dcr9 data control register (dcd0 to 3: $02c to $02f) (dcr0 to 9: $030 to $039) correspondence between ports and dcd/dcr bits 0 1 dcd0 dcd1 dcd2 dcd3 dcr0 dcr1 dcr2 dcr3 dcr4 dcr5 dcr6 dcr7 dcr8 dcr9 off (high-impedance) on bits 0 to 3 cmos buffer on/off selection register name d 3 d 7 d 11 not used r0 3 r1 3 r2 3 r3 3 r4 3 r5 3 r6 3 not used r8 3 r9 3 bit 3 d 2 d 6 d 10 not used r0 2 r1 2 r2 2 r3 2 r4 2 r5 2 r6 2 r7 2 r8 2 r9 2 bit 2 d 1 d 5 d 9 d 13 r0 1 r1 1 r2 1 r3 1 r4 1 r5 1 r6 1 r7 1 r8 1 r9 1 bit 1 d 0 d 4 d 8 d 12 r0 0 r1 0 r2 0 r3 0 r4 0 r5 0 r6 0 r7 0 r8 0 r9 0 bit 0 dcd03? dcd23, dcr03? dcr63, dcr83? dcr93 dcd02? dcd22, dcr02? dcr92 dcd01? dcd31, dcr01? dcr91 dcd00? dcd30, dcr00? dcr90 figure 28 data control registers (dcd, dcr)
hd404369 series 50 bit initial value read/write bit name 3 0 w pmrb3 2 0 w pmrb2 0 0 w pmrb0 1 0 w pmrb1 pmrb0 0 1 d 0 / int 0 mode selection d 0 int 0 port mode register b (pmrb: $024) pmrb1 0 1 d 1 / int 1 mode selection d 1 int 1 pmrb2 0 1 d 2 /evnb mode selection d 2 evnb pmrb3 0 1 d 4 / stopc mode selection d 4 stopc * note: pmrb3 is reset to 0 only by reset input. when stopc is input in stop mode, pmrb3 is not reset but retains its value. * figure 29 port mode register b (pmrb) bit initial value read/write bit name 3 0 w pmra3 2 0 w pmra2 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r0 2 /so mode selection r0 2 so port mode register a (pmra: $004) pmra1 0 1 r0 1 /si mode selection r0 1 si pmra2 0 1 r0 3 /toc mode selection r0 3 toc pmra3 0 1 d 3 /buzz mode selection d 3 buzz figure 30 port mode register a (pmra)
hd404369 series 51 bit initial value read/write bit name 3 0 w smr3 2 0 w smr2 0 0 w smr0 1 0 w smr1 serial mode register (smr: $005) smr2 smr0 smr1 smr3 0 1 r0 0 / sck mode selection r0 0 sck transmit clock selection. refer to figure 62 in the serial interface section. figure 31 serial mode register (smr) bit initial value read/write bit name 3 0 w amr13 2 0 w amr12 0 0 w amr10 1 0 w amr11 amr10 0 1 an 0 a/d mode register 1 (amr1: $019) amr11 0 1 an 1 amr12 0 1 r3 2 /an 2 mode selection r3 2 an 2 amr13 0 1 r3 3 /an 3 mode selection r3 3 an 3 r3 0 /an 0 mode selection r3 0 r3 1 /an 1 mode selection r3 1 figure 32 a/d mode register 1 (amr1)
hd404369 series 52 bit initial value read/write bit name 3 ? ? not used 2 0 w amr22 0 0 w amr20 1 0 w amr21 amr20 0 1 67 t cyc a/d mode register 2 (amr2: $01a) amr21 0 1 an 4 ?n 7 amr22 0 1 r5/an 8 ?n 11 pin selection r5 an 8 ?n 11 conversion time 34 t cyc r4/an 4 ?n 7 pin selection r4 figure 33 a/d mode register 2 (amr2) bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 cmos buffer on/off selection for pin r0 2 /so miscellaneous register (mis: $00c) 0 1 pmos active pmos off refer to figure 15 in the operation modes section. t rc selection. mis3 0 1 pull-up mos on/off selection pull-up mos off pull-up mos on (refer to table 21) mis1 mis0 figure 34 miscellaneous register (mis)
hd404369 series 53 prescalers the mcu has the following two prescalers, s and w. the prescaler operating conditions are listed in table 24, and the prescaler output supply is shown in figure 35. the timer a? input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. prescaler operation prescaler s: 11-bit counter that inputs the system clock signal. after being reset to $000 by mcu reset, prescaler s divides the system clock. prescaler s keeps counting, except in watch and subactive modes and at mcu reset. prescaler w: five-bit counter that inputs the x1 input clock signal (32-khz crystal oscillation) divided by eight. after being reset to $00 by mcu reset, prescaler w divides the input clock. prescaler w can be reset by software. table 24 prescaler operating conditions prescaler input clock reset conditions stop conditions prescaler s system clock (in active and standby mode), subsystem clock (in subactive mode) mcu reset mcu reset, stop mode, watch mode prescaler w 32-khz crystal oscillation mcu reset, software mcu reset, stop mode subsystem clock prescaler w timer a timer b timer c serial alarm output circuit system clock prescaler s clock selector f x /8 f x /4 or f x /8 figure 35 prescaler output supply
hd404369 series 54 timers the mcu has four timer/counters (a to c). timer a: free-running timer timer b: multifunction timer timer c: multifunction timer timer a is an 8-bit free-running timer. timers b and c are 8-bit multifunction timers, whose functions are listed in table 25. the operating modes are selected by software. timer a timer a functions: timer a has the following functions. free-running timer clock time-base the block diagram of timer a is shown in figure 36. timer a operations: free-running timer operation: the input clock for timer a is selected by timer mode register a (tma: $008). timer a is reset to $00 by mcu reset and incremented at each input clock. if an input clock is applied to timer a after it has reached $ff, an overflow is generated, and timer a is reset to $00. the overflow sets the timer a interrupt request flag (ifta: $001, bit 2). timer a continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. clock time-base operation: timer a is used as a clock time-base by setting bit 3 (tma3) of timer mode register a (tma: $008) to 1. the prescaler w output is applied to timer a, and timer a generates interrupts at the correct timing based on the 32.768-khz crystal oscillation. in this case, prescaler w and timer a can be reset to $00 by software. registers for timer a operation: timer a operating modes are set by the following registers. timer mode register a (tma: $008): four-bit write-only register that selects timer a? operating mode and input clock source as shown in figure 37.
hd404369 series 55 table 25 timer functions functions timer a timer b timer c clock source prescaler s available available available prescaler w available external event available timer functions free-running available available available time-base available event counter available reload available available watchdog available input capture available timer output pwm available note: ?implies not available. 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 t wcyc f t wcyc per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? w w figure 36 timer a block diagram
hd404369 series 56 bit initial value read/write bit name 3 0 w tma3 2 0 w tma2 0 0 w tma0 1 0 w tma1 timer mode register a (tma: $008) 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pss pss pss pss pss pss pss pss psw psw psw psw psw operating mode timer a mode tma3 tma1 tma2 tma0 source prescaler 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc input clock frequency 0 1 1 32t wcyc 16t wcyc 8t wcyc 2t wcyc 1/2t wcyc time-base mode 0 0 1 1 0 1 1 inhibited psw and tca reset notes: 1. 2. 3. t wcyc = 244.14 m s (when a 32.768-khz crystal oscillator is used) timer counter overflow output period (seconds) = input clock period (seconds) 256. the division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. don't care figure 37 timer mode register a (tma)
hd404369 series 57 timer b timer b functions: timer b has the following functions. free-running/reload timer external event counter input capture timer the block diagram for each operation mode of timer b is shown in figures 38 and 39. timer b operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register b1 (tmb1: $009). timer b is initialized to the value set in timer write register b (twbl: $00a, twbu: $00b) by software and incremented by one at each clock input. if an input clock is applied to timer b after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer b is initialized to its initial value set in timer write register b; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer b interrupt request flag (iftb: $002, bit 0). iftb is reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer b is used as an external event counter by selecting the external event input as an input clock source. in this case, pin d 2 /evnb must be set to evnb by port mode register b (pmrb: $024). either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by timer mode register 2 (tmb2: $026). when both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. timer b is incremented by one at each detection edge selected by timer mode register 2 (tmb2: $026). the other operation is basically the same as the free-running/reload timer operation. input capture timer operation: the input capture timer counts the clock cycles between trigger edges input to pin evnb. either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by timer mode register 2 (tmb2: $026). when a trigger edge is input to evnb, the count of timer b is written to timer read register b (trbl: $00a, trbu: $00b), and the timer b interrupt request flag (iftb: $002, bit 0) and the input capture status flag (icsf: $021, bit 0) are set. timer b is reset to $00, and then incremented again. while icsf is set, if a trigger input edge is applied to timer b, or if timer b generates an overflow, the input capture error flag (icef: $021, bit 1) is set. icsf and icef are reset to 0 by mcu reset or by writing 0.
hd404369 series 58 timer counter b (tcb) ? 2 ? 4 ? 8 ? 32 ? 128 ? 512 ? 2048 timer mode register b2 (tmb2) evnb selector system clock ? per prescaler s (pss) 2 edge detector edge detection control signal 3 timer write register b lower (twbl) timer mode register b1 (tmb1) timer write register b upper (twbu) clock free-running timer control signal timer read register b lower (trbl) interrupt request flag of timer b (iftb) timer read register b upper (trbu) overflow internal data bus figure 38 timer b free-running and reload operation block diagram
hd404369 series 59 timer counter b (tcb) internal data bus ? 2 ? 4 ? 8 ? 32 ? 128 ? 512 ? 2048 timer mode register b2 (tmb2) evnb selector system clock ? per prescaler s (pss) 2 edge detector edge detection control signal 3 timer mode register b1 (tmb1) clock input capture timer control signal timer read register b lower (trbl) interrupt request flag of timer b (iftb) timer read register b upper (trbu) overflow read signal input capture status flag (icsf) input capture error flag (icef) error controller figure 39 timer b input capture operation block diagram registers for timer b operation: by using the following registers, timer b operation modes are selected and the timer b count is read and written. ? timer mode register b1 (tmb1: $009) ? timer mode register b2 (tmb2: $026) ? timer write register b (twbl: $00a, twbu: $00b) ? timer read register b (trbl: $00a, trbu: $00b) ? port mode register b (pmrb: $024)
hd404369 series 60 timer mode register b1 (tmb1: $009): four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 40. it is reset to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register b1 write instruction. setting timer b? initialization by writing to timer write register b (twbl: $00a, twbu: $00b) must be done after a mode change becomes valid. when selecting the input capture timer operation, select the internal clock as the input clock source. bit initial value read/write bit name 3 0 w tmb13 2 0 w tmb12 0 0 w tmb10 1 0 w tmb11 timer mode register b1 (tmb1: $009) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmb12 tmb10 tmb11 input clock period and input clock source d 2 /evnb (external event input) tmb13 0 1 free-running/reload timer selection free-running timer reload timer figure 40 timer mode register b1 (tmb1) timer mode register b2 (tmb2: $026): three-bit write-only register that selects the detection edge of signals input to pin evnb and input capture operation as shown in figure 41. it is reset to $0 by mcu reset. timer write register b (twbl: $00a, twbu: $00b): write-only register consisting of the lower digit (twbl) and the upper digit (twbu). the lower digit is reset to $0 by mcu reset, but the upper digit value is invalid (figures 42 and 43). timer b is initialized by writing to timer write register b (twbl: $00a, twbu: $00b). in this case, the lower digit (twbl) must be written to first, but writing only to the lower digit does not change the timer b value. timer b is initialized to the value in timer write register b at the same time the upper digit (twbu) is written to. when timer write register b is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer b.
hd404369 series 61 timer read register b (trbl: $00a, trbu: $00b): read-only register consisting of the lower digit (trbl) and the upper digit (trbu) that holds the count of the timer b upper digit (figures 44 and 45). the upper digit (trbu) must be read first. at this time, the count of the timer b upper digit is obtained, and the count of the timer b lower digit is latched to the lower digit (trbl). after this, by reading trbl, the count of timer b when trbu is read can be obtained. when the input capture timer operation is selected and if the count of timer b is read after a trigger is input, either the lower or upper digit can be read first. port mode register b (pmrb: $024): write-only register that selects d 2 /evnb pin function as shown in figure 46. it is reset to $0 by mcu reset. bit initial value read/write bit name 3 ? ? not used 2 0 w tmb22 0 0 w tmb20 1 0 w tmb21 timer mode register b2 (tmb2: $026) tmb21 0 1 tmb20 0 1 0 1 evnb edge detection selection no detection falling edge detection rising edge detection rising and falling edge detection tmb22 0 1 free-running/reload and input capture selection free-running/reload input capture figure 41 timer mode register b2 (tmb2) bit initial value read/write bit name 3 0 w twbl3 2 0 w twbl2 0 0 w twbl0 1 0 w twbl1 timer write register b (lower digit) (twbl: $00a) figure 42 timer write register b lower digit (twbl)
hd404369 series 62 bit initial value read/write bit name 3 undefined w twbu3 2 undefined w twbu2 0 undefined w twbu0 1 undefined w twbu1 timer write register b (upper digit) (twbu: $00b) figure 43 timer write register b upper digit (twbu) bit initial value read/write bit name 3 undefined r trbl3 2 undefined r trbl2 0 undefined r trbl0 1 undefined r trbl1 timer read register b (lower digit) (trbl: $00a) figure 44 timer read register b lower digit (trbl) bit initial value read/write bit name 3 undefined r trbu3 2 undefined r trbu2 0 undefined r trbu0 1 undefined r trbu1 timer read register b (upper digit) (trbu: $00b) figure 45 timer read register b upper digit (trbu)
hd404369 series 63 bit initial value read/write bit name 3 0 w pmrb3 2 0 w pmrb2 0 0 w pmrb0 1 0 w pmrb1 pmrb0 0 1 d 0 / int 0 mode selection d 0 int 0 port mode register b (pmrb: $024) pmrb1 0 1 d 1 / int 1 mode selection d 1 int 1 pmrb2 0 1 d 2 /evnb mode selection d 2 evnb pmrb3 0 1 d 4 / stopc mode selection d 4 stopc * note: pmrb3 is reset to 0 only by reset input. when stopc is input in stop mode, pmrb3 is not reset but retains its value. * figure 46 port mode register b (pmrb)
hd404369 series 64 timer c timer c functions : timer c has the following functions. free-running/reload timer watchdog timer timer output operation (pwm output) the block diagram of timer c is shown in figure 47. timer counter c (tcc) ? 2 ? 4 ? 8 ? 32 ? 128 ? 512 ? 1024 ? 2048 port mode register a (pmra) selector system clock ? per prescaler s (pss) 3 timer write register c lower (twcl) timer mode register c (tmc) timer write register c upper (twcu) clock free-running timer control signal timer read register c lower (trcl) interrupt request flag of timer c (iftc) timer read register c upper (trcu) overflow toc timer output control signal watchdog timer controller watchdog on flag (wdon) system reset signal internal data bus timer output control logic figure 47 timer c block diagram
hd404369 series 65 timer c operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register c (tmc: $00d). timer c is initialized to the value set in timer write register c (twcl: $00e, twcu: $00f) by software and incremented by one at each clock input. if an input clock is applied to timer c after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer c is initialized to its initial value set in timer write register c; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer c interrupt request flag (iftc: $002, bit 2). iftc is reset by software or mcu reset. refer to figure 3 and table 1 for details. watchdog timer operation: timer c is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (wdon: $020, bit 1) to 1. if a program routine runs out of control and an overflow is generated, the mcu is reset. the watchdog timer operation flowchart is shown in figure 48. program run can be controlled by initializing timer c by software before it reaches $ff. timer output operation: the pwm output modes can be selected for timer c by setting port mode register a (pmra: $004). by selecting the timer output mode, pin r0 3 /toc is set to toc. the output from toc is reset low by mcu reset. pwm output: when pwm output mode is selected, timer c provides the variable-duty pulse output function. the output waveform differs depending on the contents of timer mode register c (tmc: $00d) and timer write register c (twcl: $00e, twcu: $00f). the output waveform is shown in figure 49. $ff + 1 $00 timer c count value overflow time cpu operation normal operation timer c clear normal operation timer c clear program runaway normal operation reset figure 48 watchdog timer operation flowchart
hd404369 series 66 t (n + 1) t 256 t t (256 ?n) tmc3 = 0 (free-running timer) tmc3 = 1 (reload timer) notes: t: input clock period supplied to counter. (the clock source and system clock division ratio are determined by timer mode register c.) n: value of timer write register c. (when n = 255 ($ff), pwm output is fixed low.) figure 49 pwm output waveform registers for timer c operation: by using the following registers, timer c operation modes are selected and the timer c count is read and written. ? timer mode register c (tmc: $00d) ? port mode register a (pmra: $004) ? timer write register c (twcl: $00e, twcu: $00f) ? timer read register c (trcl: $00e, trcu: $00f) timer mode register c (tmc: $00d): four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 50. it is reset to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register c write instruction. setting timer c? initialization by writing to timer write register c (twcl: $00e, twcu: $00f) must be done after a mode change becomes valid.
hd404369 series 67 bit initial value read/write bit name 3 0 w tmc3 2 0 w tmc2 0 0 w tmc0 1 0 w tmc1 timer mode register c (tmc: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc2 tmc0 tmc1 input clock period tmc3 0 1 free-running/reload timer selection free-running timer reload timer 1024t cyc figure 50 timer mode register c (tmc) port mode register a (pmra: $004): write-only register that selects r0 3 /toc pin function as shown in figure 51. it is reset to $0 by mcu reset. timer write register c (twcl: $00e, twcu: $00f): write-only register consisting of the lower digit (twcl) and the upper digit (twcu) as shown in figures 52 and 53. the operation of timer write register c is basically the same as that of timer write register b (twbl: $00a, twbu: $00b). timer read register c (trcl: $00e, trcu: $00f): read-only register consisting of the lower digit (trcl) and the upper digit (trcu) that holds the count of the timer c upper digit (figures 54 and 55). the operation of timer read register c is basically the same as that of timer read register b (trbl: $00a, trbu: $00b).
hd404369 series 68 bit initial value read/write bit name 3 0 w pmra3 2 0 w pmra2 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r0 2 /so mode selection r0 2 so port mode register a (pmra: $004) pmra1 0 1 r0 1 /si mode selection r0 1 si pmra2 0 1 r0 3 /toc mode selection r0 3 toc pmra3 0 1 d 3 /buzz mode selection d 3 buzz figure 51 port mode register a (pmra) bit initial value read/write bit name 3 0 w twcl3 2 0 w twcl2 0 0 w twcl0 1 0 w twcl1 timer write register c (lower digit) (twcl: $00e) figure 52 timer write register c lower digit (twcl) bit initial value read/write bit name 3 undefined w twcu3 2 undefined w twcu2 0 undefined w twcu0 1 undefined w twcu1 timer write register c (upper digit) (twcu: $00f) figure 53 timer write register c upper digit (twcu)
hd404369 series 69 bit initial value read/write bit name 3 undefined r trcl3 2 undefined r trcl2 0 undefined r trcl0 1 undefined r trcl1 timer read register c (lower digit) (trcl: $00e) figure 54 timer read register c lower digit (trcl) bit initial value read/write bit name 3 undefined r trcu3 2 undefined r trcu2 0 undefined r trcu0 1 undefined r trcu1 timer read register c (upper digit) (trcu: $00f) figure 55 timer read register c upper digit (trcu) notes on use when using the timer output as pwm output, note the following point. from the update of the timer write register until the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 26. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle. in this case, the lower digit (twcl) must be written to first, bit writing only to the lower digit does not change the timer c value. timer c is changed to the value in timer write register b at the same time the upper digit (twcu) is written to.
hd404369 series 70 table 26 pwm output following update of timer write register pwm output mode timer write register is updated during high pwm output timer write register is updated during low pwm output reload timer write register updated to value n interrupt request t t (255 ?n) t timer write register updated to value n interrupt request t t (255 ?n) t
hd404369 series 71 alarm output function the mcu has a built-in pulse output function called buzz. the pulse frequency can be selected from the prescaler s? outputs, and the output frequency depends on the state of port mode register c (pmrc: $025). the duty cycle of the pulse output is fixed at 50%. port mode register c (pmrc: $025): four-bit write-only register that selects the alarm frequencies as shown in figure 57. it is reset to $0 by mcu reset. port mode register a (pmra: $004): four-bit write-only register that selects d 3 /buzz pin function as shown in figure 51. it is reset to $0 by mcu reset. internal data bus ? 256 ? 512 ? 1024 ? 2048 selector system clock per prescaler s (pss) 2 alarm output control signal buzz alarm output controller port mode register c (pmrc) port mode register a (pmra) figure 56 alarm output function block diagram
hd404369 series 72 bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 undefined w pmrc1 port mode register c (pmrc: $025) pmrc1 0 1 output level control in idle states low level high level pmrc0 0 1 serial clock division ratio prescaler output divided by 2 prescaler output divided by 4 pmrc3 0 1 0 1 pmrc2 system clock divisor ? 2048 ? 1024 ? 512 ? 256 0 1 figure 57 port mode register c (pmrc)
hd404369 series 73 serial interface the serial interface serially transfers and receives 8-bit data, and includes the following features. multiple transmit clock sources ? external clock ? internal prescaler output clock ? system clock output level control in idle states four registers, an octal counter, and a selector are also configured for the serial interface as follows. ? serial data register (srl: $006, sru: $007) ? serial mode register (smr: $005) ? port mode register a (pmra: $004) ? port mode register c (pmrc: $025) ? miscellaneous register (mis: $00c) ? octal counter (oc) ? selector the block diagram of the serial interface is shown in figure 58.
hd404369 series 74 internal data bus ? 2 ? 8 ? 32 ? 128 ? 512 ? 2048 port mode register c (pmrc) sck selector system clock per prescaler s (pss) idle controller 3 serial mode register (smr) clock serial data register (sr) serial interrupt request flag (ifs) selector 1/2 1/2 si so octal counter (oc) i/o controller transfer control signal figure 58 serial interface block diagram serial interface operation selecting and changing the operating mode: table 27 lists the serial interface? operating modes. to select an operating mode, use one of these combinations of port mode register a (pmra: $004) and the serial mode register (smr: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to the serial mode register. note that the serial interface is initialized by writing data to the serial mode register. refer to the following serial mode register section for details. pin setting: the r0 0 / sck pin is controlled by writing data to the serial mode register (smr: $005). the r0 1 /si and r0 2 /so pins are controlled by writing data to port mode register a (pmra: $004). refer to the following registers for serial interface section for details. transmit clock source setting: the transmit clock source is set by writing data to the serial mode register (smr: $005) and port mode register c (pmrc: $025). refer to the following registers for serial interface section for details. data setting: transmit data is set by writing data to the serial data register (srl: $006, sru, $007). receive data is obtained by reading the contents of the serial data register. the serial data is shifted by the transmit clock and is input from or output to an external system.
hd404369 series 75 the output level of the so pin is invalid until the first data is output after mcu reset, or until the output level control in idle states is performed. transfer control: the serial interface is activated by the sts instruction. the octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. when the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial interrupt request flag (ifs: $003, bit 2) is set, and the transfer stops. when the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t cyc to 8192t cyc by setting bits 0 to 2 (smr0?smr2) of serial mode register (smr: $005) and bit 0 (pmrc0) of port mode register c (pmrc: $025) as listed in table 28. operating states: the serial interface has the following operating states; transitions between them are shown in figure 59. ? sts wait state ? transmit clock wait state ? transfer state ? continuous clock output state (only in internal clock mode) sts wait state: the serial interface enters sts wait state by mcu reset (00, 10 in figure 59). in sts wait state, the serial interface is initialized and the transmit clock is ignored. if the sts instruction is then executed (01, 11), the serial interface enters transmit clock wait state. transmit clock wait state: transmit clock wait state is the period between the sts execution and the falling edge of the first transmit clock. in transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register, and puts the serial interface in transfer state. however, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). the serial interface enters sts wait state by writing data to the serial mode register (smr: $005) (04, 14) in transmit clock wait state. transfer state: transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. in transfer state, the input of eight clocks or the execution of the sts instruction sets the octal counter to 000, and the serial interface enters another state. when the sts instruction is executed (05, 15), transmit clock wait state is entered. when eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and sts wait state is entered (13) in internal clock mode. in internal clock mode, the transmit clock stops after outputting eight clocks. in transfer state, writing data to the serial mode register (smr: $005) (06, 16) initializes the serial interface, and sts wait state is entered. if the state changes from transfer to another state, the serial interrupt request flag (ifs: $003, bit 2) is set by the octal counter that is reset to 000. continuous clock output state (only in internal clock mode): continuous clock output state is entered only in internal clock mode. in this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the sck pin.
hd404369 series 76 when bits 0 and 1 (pmra0, pmra1) of port mode register a (pmra: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. if the serial mode register (smr: $005) is written to in continuous clock output mode (18), sts wait state is entered. output level control in idle states: in idle states, that is, sts wait state and transmit clock wait state, the output level of the so pin can be controlled by setting bit 1 (pmrc1) of port mode register c (pmrc: $025) to 0 or 1. the output level control example is shown in figure 60. note that the output level cannot be controlled in transfer state. transmit clock error detection (in external clock mode): the serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. a transmit clock error of this type can be detected as shown in figure 61. table 27 serial interface operating modes smr pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode table 28 serial transmit clock (prescaler output) pmrc smr bit 0 bit 2 bit 1 bit 0 prescaler division ratio transmit clock frequency 0000 ? 2048 4096t cyc 1 ? 512 1024t cyc 10 ? 128 256t cyc 1 ? 32 64t cyc 10 0 ? 8 16t cyc 1 ? 24t cyc 1000 ? 4096 8192t cyc 1 ? 1024 2048t cyc 10 ? 256 512t cyc 1 ? 64 128t cyc 10 0 ? 16 32t cyc 1 ? 48t cyc
hd404369 series 77 if more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (ifs: $003, bit 2) is set, and transmit clock wait state is entered. at the falling edge of the next normal clock signal, the transfer state is entered. after the transfer completion processing is performed and ifs is reset, writing to the serial mode register (smr: $005) changes the state from transfer to sts wait. at this time ifs is set again, and therefore the error can be detected. notes on use: initialization after writing to registers: if port mode register a (pmra: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode register (smr: $005) again. serial interrupt request flag (ifs: $003, bit 2) set: if the state is changed from transfer to another by writing to the serial mode register (smr: $005) or executing the sts instruction during the first low pulse of the transmit clock, the serial interrupt request flag is not set. to set the serial interrupt request flag, serial mode register write or sts instruction execution must be programmed to be executed after confirming that the sck pin is at 1, that is, after executing the input instruction to port r0. sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) trans fer state (octal counter 1 000) mcu reset 00 smr write 04 sts instruction 01 transmit clock 02 8 transmit clocks 03 sts instruction (ifs 1) 05 ? smr write (ifs 1) 06 ? external clock mode sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter 1 000) smr write 14 sts instruction 11 transmit clock 12 15 sts instruction (ifs 1) ? 8 transmit clocks 13 internal clock mode continuous clock output state (pmra 0, 1 = 0, 0) smr write 18 transmit clock 17 16 note: refer to the operating states section for the corresponding encircled numbers. mcu reset 10 ? smr write (ifs 1) figure 59 serial interface state transitions
hd404369 series 78 state mcu reset pmra write smr write pmrc write srl, sru write sts instruction sck pin (input) so pin ifs sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission undefined lsb msb flag reset at transfer completion external clock mode state mcu reset pmra write smr write pmrc write srl, sru write sts instruction sck pin (output) so pin ifs sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states undefined lsb msb flag reset at transfer completion internal clock mode figure 60 example of serial interface operation sequence
hd404369 series 79 transfer completion (ifs 1) interrupts inhibited ifs 0 smr write ifs = 1 transmit clock error processing normal termination ? ? yes no transmit clock error detection flowchart transmit clock error detection procedure state sck pin (input) transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when smr is written, ifs is set. flag set because octal counter reaches 000 flag reset at transfer completion smr write ifs 12 3 45678 figure 61 transmit clock error detection registers for serial interface the serial interface operation is selected, and serial data is read and written by the following registers. ? serial mode register (smr: $005) ? serial data register (srl: $006, sru: $007) ? port mode register a (pmra: $004) ? port mode register c (pmrc: $025) ? miscellaneous register (mis: $00c)
hd404369 series 80 serial mode register (smr: $005): this register has the following functions (figure 62). r0 0 / sck pin function selection transmit clock selection prescaler division ratio selection serial interface initialization serial mode register (smr: $005) is a 4-bit write-only register. it is reset to $0 by mcu reset. a write signal input to serial mode register (smr: $005) discontinues the input of the transmit clock to the serial data register and octal counter, and the octal counter is reset to 000. therefore, if a write is performed during data transfer, the serial interrupt request flag (ifs: $003, bit 2) is set. written data is valid from the second instruction execution cycle after the write operation, so the sts instruction must be executed at least two cycles after that. bit initial value read/write bit name 3 0 w smr3 2 0 w smr2 0 0 w smr0 1 0 w smr1 serial mode register (smr: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 smr2 smr0 smr1 smr3 0 1 r0 0 / sck mode selection r0 0 sck sck output output input clock source external clock ? prescaler division ratio refer to table 28 prescaler system clock figure 62 serial mode register (smr)
hd404369 series 81 port mode register c (pmrc: $025): this register has the following functions (figure 63). prescaler division ratio selection output level control in idle states port mode register c (pmrc: $025) is a 4-bit write-only register. it cannot be written during data transfer. by setting bit 0 (pmrc0) of this register, the prescaler division ratio is selected. bit 0 (pmrc0) can be reset to 0 by mcu reset. by setting bit 1 (pmrc1), the output level of the so pin is controlled in idle states. the output level changes at the same time that pmrc1 is written to. bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 undefined w pmrc1 port mode register c (pmrc: $025) pmrc1 0 1 output level control in idle states low level high level pmrc0 0 1 serial clock division ratio prescaler output divided by 2 prescaler output divided by 4 alarm output function. refer to figure 57. figure 63 port mode register c (pmrc)
hd404369 series 82 serial data register (srl: $006, sru: $007): this register has the following functions (figures 64 and 65). transmission data write and shift receive data shift and read writing data in this register is output from the so pin, lsb first, synchronously with the falling edge of the transmit clock; data is input, lsb first, through the si pin at the rising edge of the transmit clock. input/output timing is shown in figure 66. data cannot be read or written during serial data transfer. if a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. bit initial value read/write bit name 3 undefined r/w sr3 2 undefined r/w sr2 0 undefined r/w sr0 1 undefined r/w sr1 serial data register (lower digit) (srl: $006) figure 64 serial data register (srl) bit initial value read/write bit name 3 undefined r/w sr7 2 undefined r/w sr6 0 undefined r/w sr4 1 undefined r/w sr5 serial data register (upper digit) (sru: $007) figure 65 serial data register (sru) lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 66 serial interface output timing
hd404369 series 83 port mode register a (pmra: $004): this register has the following functions (figure 67). r0 1 /si pin function selection r0 2 /so pin function selection port mode register a (pmra: $004) is a 4-bit write-only register, and is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w pmra3 2 0 w pmra2 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r0 2 /so mode selection r0 2 so port mode register a (pmra: $004) pmra1 0 1 r0 1 /si mode selection r0 1 si pmra2 0 1 r0 3 /toc mode selection r0 3 toc pmra3 0 1 d 3 /buzz mode selection d 3 buzz figure 67 port mode register a (pmra)
hd404369 series 84 miscellaneous register (mis: $00c): this register has the following functions (figure 68). r0 2 /so pin pmos control miscellaneous register (mis: $00c) is a 4-bit write-only register and is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 cmos buffer on/off selection for pin r0 2 /so miscellaneous register (mis: $00c) 0 1 pmos active pmos off refer to figure 15 in the operation modes section. t rc selection. mis3 0 1 pull-up mos on/off selection pull-up mos off pull-up mos on (refer to table 21) mis1 mis0 figure 68 miscellaneous register (mis)
hd404369 series 85 a/d converter the mcu has a built-in a/d converter that uses a sequential comparison method with a resistor ladder. it can measure twelve analog inputs with 8-bit resolution. the block diagram of the a/d converter is shown in figure 69. i ad off flag (iaof) selector 4 a/d channel register (acr) a/d mode register 2 (amr2) a/d mode register 1 (amr1) a/d interrupt request flag (ifad) encoder a/d data register (adru, l) a/d start flag (adsf) d/a av cc av ss operating mode signal (1 in stop, watch, and subactive modes) internal data bus + ? comp a/d controller an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 8 an 9 an 10 an 11 control signal for conversion time 4 2 figure 69 a/d converter block diagram
hd404369 series 86 registers for a/d converter operation a/d mode register 1 (amr1: $019): four-bit write-only register which selects digital or analog ports, as shown in figure 70. bit initial value read/write bit name 3 0 w amr13 2 0 w amr12 0 0 w amr10 1 0 w amr11 amr10 0 1 an 0 a/d mode register 1 (amr1: $019) amr11 0 1 an 1 amr12 0 1 r3 2 /an 2 mode selection r3 2 an 2 amr13 0 1 r3 3 /an 3 mode selection r3 3 an 3 r3 0 /an 0 mode selection r3 0 r3 1 /an 1 mode selection r3 1 figure 70 a/d mode register 1 (amr1) a/d mode register 2 (amr2: $01a): three-bit write-only register which is used to set the a/d conversion period and to select digital or analog ports. bit 0 of the a/d mode register selects the a/d conversion period, and bits 1 and 2 select ports r4?5 as pins an 4 ?n 11 in 4-pin units (figure 71). bit initial value read/write bit name 3 ? ? not used 2 0 w amr22 0 0 w amr20 1 0 w amr21 amr20 0 1 67 t cyc a/d mode register 2 (amr2: $01a) amr21 0 1 an 4 ?n 7 amr22 0 1 r5/an 8 ?n 11 pin selection r5 an 8 ?n 11 conversion time 34 t cyc r4/an 4 ?n 7 pin selection r4 figure 71 a/d mode register 2 (amr2)
hd404369 series 87 a/d channel register (acr: $016): four-bit write-only register which indicates analog input pin information, as shown in figure 72. bit initial value read/write bit name 3 0 w acr3 2 0 w acr2 0 0 w acr0 1 0 w acr1 a/d channel register (acr: $016) 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 analog input selection an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 8 an 9 an 10 an 11 not used acr3 acr1 acr2 acr0 0 1 1 0 0 1 1 1 don? care. don? care. figure 72 a/d channel register (acr)
hd404369 series 88 a/d start flag (adsf: $02c, bit 2): one-bit flag that initiates a/d conversion when set to 1. at the completion of a/d conversion, the converted data is stored in the a/d data register and the a/d start flag is cleared. refer to figure 73. bit initial value read/write bit name 3 0 r/w dton 2 0 r/w adsf 0 0 r/w lson 1 0 w wdon a/d start flag (adsf: $020, bit 2) refer to the description of operating modes dton refer to the description of timers wdon refer to the description of operating modes lson 0 1 a/d conversion completed a/d conversion started a/d start flag (adsf) figure 73 a/d start flag (adsf) i ad off flag (iaof: $021, bit 2): by setting the i ad off flag to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode, as shown in figure 74. bit initial value read/write bit name 3 0 r/w rame 2 0 r/w iaof 0 0 r/w icsf 1 0 r/w icef i ad off flag (iaof: $021, bit 2) refer to the description of operating modes rame refer to the description of timers icef refer to the description of timers icsf 0 1 i ad current flows i ad current is cut off i ad off flag (iaof) figure 74 i ad off flag (iaof)
hd404369 series 89 a/d data register (adrl: $017, adru: $018): eight-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. this register is not cleared by reset. after the completion of a/d conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 75, 76, and 77). 3210 msb lsb 3210 bit 0 bit 7 adru: $018 adrl: $017 figure 75 a/d data registers (adru, adrl) bit initial value read/write bit name 3 0 r adrl3 2 0 r adrl2 0 0 r adrl0 1 0 r adrl1 a/d data register (lower digit) (adrl: $017) figure 76 a/d data register lower digit (adrl) bit initial value read/write bit name a/d data register (upper digit) (adru: $018) 2 0 r adru2 1 0 r adru1 0 0 r adru0 3 1 r adru3 figure 77 a/d data register upper digit (adru)
hd404369 series 90 notes on usage use the sem or semd instruction for writing to the a/d start flag (adsf) do not write to the a/d start flag during a/d conversion data in the a/d data register during a/d conversion is undefined since the operation of the a/d converter is based on the clock from the system oscillator, the a/d converter does not operate in stop, watch, or subactive mode. in addition, to save power while in these modes, all current flowing through the converter? resistance ladder is cut off. if the power supply for the a/d converter is to be different from v cc , connect a 0.1- m f bypass capacitor between the av cc and av ss pins. (however, this is not necessary when the av cc pin is directly connected to the v cc pin.) the contents of the a/d data register are not guaranteed during a/d conversion. to ensure that the a/d converter operates stably, do not execute port output instructions during a/d conversion. the port data register (pdr) is initialized to 1 by an mcu reset. at this time, if pull-up mos is selected as active by bit 3 of the miscellaneous register (mis3), the port will be pulled up to v cc . when using a shared r port/analog input pin as an input pin, clear pdr to 0. otherwise, if pull-up mos is selected by mis3 and pdr is set to 1, a pin selected by a/d mode register 1 or 2 (amr1 or amr2) as an analog pin will remain pulled up (figure 78). v cc v cc hlt mis3 dcr pdr cpu input input control signal acr a/d input a/d channel register value amr a/d mode register value figure 78 r port/analog multiplexed pin circuit
hd404369 series 91 pin description in prom mode the hd407a4369 is a prom version of a ztat ? microcomputer. in prom mode, the mcu stops operating, thus allowing the user to program the on-chip prom. pin number mcu mode prom mode dp-64s fp-64b fp-64a pin i/o pin i/o 1 5957r6 0 i/o 2 6058r6 1 i/o 3 6159r6 2 i/o 4 6260r6 3 i/o 5 6361r7 0 i/o 6 6462r7 1 i/o 7 1 63 r7 2 i/o 8 2 64 r0 0 / sck i/o v cc 9 31r0 1 /si i/o v cc 1042r0 2 /so i/o o 1 i/o 1153r0 3 /toc i/o o 2 i/o 12 6 4 test i v pp 13 7 5 reset i reset i 14 8 6 osc 1 iv cc 15 9 7 osc 2 o 16 10 8 gnd gnd 17 11 9 x1 i gnd 18 12 10 x2 o 19 13 11 av ss gnd 20 14 12 r3 0 /an 0 i/o o 0 i/o 21 15 13 r3 1 /an 1 i/o o 1 i/o 22 16 14 r3 2 /an 2 i/o o 2 i/o 23 17 15 r3 3 /an 3 i/o o 3 i/o 24 18 16 r4 0 /an 4 i/o o 4 i/o 25 19 17 r4 1 /an 5 i/o m 0 i 26 20 18 r4 2 /an 6 i/o m 1 i 27 21 19 r4 3 /an 7 i/o 28 22 20 r5 0 /an 8 i/o 29 23 21 r5 1 /an 9 i/o 30 24 22 r5 2 /an 10 i/o
hd404369 series 92 pin number mcu mode prom mode dp-64s fp-64b fp-64a pin i/o pin i/o 31 25 23 r5 3 /an 11 i/o 32 26 24 av cc ? cc 33 27 25 v cc ? cc 34 28 26 d 0 / int 0 i/o o 3 i/o 35 29 27 d 1 / int 1 i/o o 4 i/o 36 30 28 d 2 /evnb i/o a 1 i 37 31 29 d 3 /buzz i/o a 2 i 38 32 30 d 4 / stopc i/o 39 33 31 d 5 i/o a 3 i 40 34 32 d 6 i/o a 4 i 41 35 33 d 7 i/o a 9 i 42 36 34 d 8 i/o v cc 43 37 35 d 9 i/o 44 38 36 d 10 i/o 45 39 37 d 11 i/o 46 40 38 d 12 i/o 47 41 39 d 13 i/o 48 42 40 r8 0 i/o ce i 49 43 41 r8 1 i/o oe i 50 44 42 r8 2 i/o a 13 i 51 45 43 r8 3 i/o a 14 i 52 46 44 r9 0 i/o 53 47 45 r9 1 i/o 54 48 46 r9 2 i/o 55 49 47 r9 3 i/o 56 50 48 r1 0 i/o a 5 i 57 51 49 r1 1 i/o a 6 i 58 52 50 r1 2 i/o a 7 i 59 53 51 r1 3 i/o a 8 i 60 54 52 r2 0 i/o a 0 i 61 55 53 r2 1 i/o a 10 i 62 56 54 r2 2 i/o a 11 i 63 57 55 r2 3 i/o a 12 i 64 58 56 ra 1 io 0 i/o notes: 1. i/o: input/output pin; i: input pin; o: output pin 2. o 0 to o 4 consist of two pins each. tie each pair together before using them.
hd404369 series 93 programming the built-in prom the mcu? built-in prom is programmed in prom mode. prom mode is set by pulling reset , m 0 , and m 1 low, as shown in figure 79. in prom mode, the mcu does not operate, but it can be programmed in the same way as any other commercial 27256-type eprom using a standard prom programmer and a 100-to-28-pin socket adapter. recommended prom programmers and socket adapters are listed in table 29. since an hmcs400-series instruction is ten bits long, the hmcs400-series mcu has a built-in conversion circuit to enable the use of a general-purpose prom programmer. this circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. this means that if, for example, 16 kwords of built-in prom are to be programmed by a general-purpose prom programmer, a 32-kbyte address space ($0000?7fff) must be specified. control signals address bus data bus v cc gnd v pp o 7 ? 0 o 7 o 6 o 5 o 4 ? 0 ce , oe a 14 ? 0 o 4 ? 0 m 0 m 1 reset v cc gnd v pp hd407a4369 prom mode pins socket adapter prom programmer figure 79 prom mode connections
hd404369 series 94 table 29 recommended prom programmers and socket adapters prom programmer socket adapter manufacture model name package manufacture model name data i/o corp 121 b dp-64s hitachi hs4369ess01h fp-64b hs4369esf01h fp-64a hs4369esh01h aval corp pkw-1000 dp-64s hitachi hs4369ess01h fp-64b hs4369esf01h fp-64a hs4369esh01h warnings 1. always specify addresses $0000 to $7fff when programming with a prom programmer. if address $8000 or higher is accessed, the prom may not be programmed or verified correctly. set all data in unused addresses to $ff. note that the plastic-package version cannot be erased and reprogrammed. 2. make sure that the prom programmer, socket adapter, and lsi are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the lsi. before starting programming, make sure that the lsi is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. prom programmers have two voltages (v pp ): 12.5 v and 21 v. remember that ztat ? devices require a v pp of 12.5 v?he 21-v setting will damage them. 12.5 v is the intel 27256 setting. programming and verification the built-in prom of the mcu can be programmed at high speed without risk of voltage stress or damage to data reliability. programming and verification modes are selected as listed in table 30. for details of prom programming, refer to the following notes on prom programming section. table 30 prom mode selection pin mode ce oe v pp o 0 ? 4 programming low high v pp data input verification high low v pp data output programming inhibited high high v pp high impedance
hd404369 series 95 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 80 and described below. register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. ap 9 ap 0 w 1 y 0 w register x register y register ram address register direct addressing ap 9 ap 0 ram address direct addressing d 9 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 0 ram address memory register addressing m 3 opcode instruction 000100 ap 8 ap 7 ap ap 5 ap 4 6 ap 3 ap 2 ap 1 ap ap ap ap ap ap ap ap 87654321 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 m 2 m 1 m 0 figure 80 ram addressing modes
hd404369 series 96 rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 81 and described below. direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ?c 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page, as shown in figure 83. this means that the execution of the br instruction on a page boundary will make the program branch to the next page. note that the hmcs400-series cross macroassembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $0000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 82. if bit 8 of the rom data is 1, eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter.
hd404369 series 97 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc pc 10 11 12 13 program counter direct addressing zero page addressing d 5 d 4 d 3 d 2 d 1 d 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10 11 12 13 program counter 00 00 0 0 0 0 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc 10 11 12 13 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 0 0 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pc pc pc 11 12 13 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc p 0 p 1 p 2 p 3 figure 81 rom addressing modes
hd404369 series 98 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referenced rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ra ra ra 10 11 12 13 b 2 b 3 b register 0 0 p 3 p 0 [p] instruction opcode p 2 p 1 ra r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern output ro 9 rom data if ro = 1 9 output registers r1, r2 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 82 p instruction
hd404369 series 99 br aaa aaa nop 256 (n ?1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 83 branching when the branch destination is on a page boundary
hd404369 series 100 instruction set the hd404369 series has 101 instructions, classified into the following 10 groups: immediate instructions register-to-register instructions ram address instructions ram register instructions arithmetic instructions compare instructions ram bit manipulation instructions rom address instructions input/output instructions control instructions
hd404369 series 101 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v 2 ?.3 to +15.0 v 3 total permissible input current ? i o 105 ma 4 total permissible output current ? i o 50 ma 5 maximum input current i o 4 ma 6, 7 30 ma 6, 8 maximum output current ? o 4 ma 7, 9 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to pin test (v pp ) of hd407a4369. 2. applies to all standard voltage pins. 3. applies to intermediate-voltage pins. 4. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to gnd. 5. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 6. the maximum input current is the maximum current flowing from each i/o pin to gnd. 7. applies to ports d 0 to d 13 , r0, r3 to r9. 8. applies to ports r1 and r2. 9. the maximum output current is the maximum current flowing from v cc to each i/o pin
hd404369 series 102 electrical characteristics dc characteristics (hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c; hd404364/HD404368/hd4043612/hd404369/hd40a4364/hd40a4368/hd40a43612/hd40a4369:v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition notes input high voltage v ih reset , sck , int 0 , int 1 , stopc , evnb 0.8v cc ? cc + 0.3 v si 0.7 v cc ? cc + 0.3 v osc 1 v cc ?0.5 v cc + 0.3 v input low voltage v il reset , sck , int 0 , int 1 , stopc , evnb ?.3 0.2v cc v si ?.3 0.3v cc v osc 1 ?.3 0.5 v output high voltage v oh sck , so, toc v cc ?0.5 v i oh = 0.5 ma output low voltage v ol sck , so, toc 0.4 v i ol = 0.4 ma i/o leakage current |i il | reset , sck , si, so, toc, osc 1 , int 0 , int 1 , stopc , evnb 1 m av in = 0 v to v cc 1 current dissipation in active mode i cc v cc 5.0 ma v cc = 5 v, f osc = 4 mhz 2 current dissipation in standby mode i sby v cc 2.0 ma v cc = 5 v, f osc = 4 mhz 3 current dissipation in subactive mode i sub v cc 100 m av cc = 5 v, 32 khz oscillator 4 current dissipation in watch mode i wtc v cc 20 m av cc = 5 v, 32 khz oscillator 4
hd404369 series 103 item symbol pins min typ max unit test condition notes current dissipation in stop mode i stop v cc 10 m av cc = 5v, x1 = gnd, x2 = open 4 stop mode retaining voltage v stop v cc 2 v notes: 1. excludes current flowing through pull-up mos and output buffers. 2. i cc is the source current when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset , test at gnd 3. i sby is the source current when no i/o current is flowing while the mcu timer is operating. test conditions: mcu: i/o reset standby mode pins: reset at v cc test at gnd d 0 ? 13 , r0?9, ra 1 at v cc 4. this is the source current when no i/o current is flowing. test conditions: pins: reset at v cc test at gnd d 0 ? 13 , r0?9, ra 1 at v cc
hd404369 series 104 i/o characteristics for standard pins (hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c; hd404364/HD404368/hd4043612/hd404369/hd40a4364/hd40a4368/hd40a43612/hd40a 4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition note input high voltage v ih d 0 ? 13 , r0, r3?9, ra 1 0.7v cc ? cc + 0.3 v input low voltage v il d 0 ? 13 , r0, r3?9, ra 1 ?.3 0.3v cc v output high voltage v oh d 0 ? 13 , r0, r3?9 v cc 0.5 v i oh = 0.5 ma output low voltage v ol d 0 ? 13 , r0, r3?9 0.4 v i ol = 1.6 ma input leakage current |i il |d 0 ? 13 , r0, r3?9, ra 1 1 m av in = 0 v to v cc 1 pull-up mos current ? pu d 0 ? 13 , r0, r3?9 30 150 300 m av cc = 5 v, v in = 0 v note: 1. output buffer current is excluded. i/o characteristics for intermediate-voltage pins (hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c; hd404364/HD404368/hd4043612/hd404369/hd40a4364/hd40a4368/hd40a43612/ hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition note input high voltage v ih r1, r2 0.7v cc ?2 v input low voltage v il r1, r2 ?.3 0.3v cc v output high voltage v oh r1, r2 11.5 v 500 k w at 12 v output low voltage v ol r1, r2 0.4 v i ol = 0.4 ma 2.0 v i ol = 15 ma, v cc = 4.5 to 5.5 v i/o leakage current |i il | r1, r2 20 m av in = 0 v to 12 v 1 note: 1. excludes output buffer current.
hd404369 series 105 a/d converter characteristics (hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c;hd404364/HD404368/hd4043612/hd404369/hd40a4364/hd40a4368/hd40a43612/hd40a 4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition notes analog supply voltage av cc av cc v cc 0.3 v cc v cc + 0.3 v 1 analog input voltage av in an 0 ?n 11 av ss ?v cc v current flowing between av cc and av ss i ad 200 m av cc = av cc = 5.0 v analog input capacitance ca in an 0 ?n 11 30 pf resolution 8 8 8 bit number of input channels 0 12 chan nel absolute accuracy 2.0 lsb conversion time 34 67 t cyc input impedance an 0 ?n 11 1 m w note: 1. connect this to v cc if the a/d converter is not used.
hd404369 series 106 standard f osc = 5 mhz version ac characteristics (hd404364/HD404368/hd4043612/hd404369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c) item symbol pins min typ max unit test condition notes clock oscillation frequency f osc osc 1 , osc 2 0.4 4 5.0 mhz 1/4 system clock division ratio 1 x1, x2 32.768 khz instruction cycle time t cyc 0.8 1 10 m s1 t subcyc 244.14 m s 32-khz oscillator, 1/8 system clock division ratio 122.07 m s 32-khz oscillator, 1/4 system clock division ratio oscillation stabilization time (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 2 oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 40 ms 2 x1, x2 2 s 2 external clock high width t cph osc 1 80 ns 3 external clock low width t cpl osc 1 80 ns 3 external clock rise time t cpr osc 1 20 ns 3 external clock fall time t cpf osc 1 20 ns 3 int 0 , int 1 , evnb high widths t ih int 0 , int 1 , evnb 2 t cyc / t subcyc 4 int 0 , int 1 , evnb low widths t il int 0 , int 1 , evnb 2 t cyc / t subcyc 4 reset low width t rstl reset 2 t cyc 5 stopc low width t stpl stopc 1 t rc 6 reset rise time t rstr reset 20 ms 5 stopc rise time t stpr stopc 20 ms 6 input capacitance c in all input pins except r1 and r2 15 pf f = 1 mhz, v in = 0 v r1, r2 30 pf f = 1 mhz, v in = 0 v
hd404369 series 107 notes: 1. when using the subsystem oscillator (32.768 khz), one of the following relationships for f osc must be applied. 0.4 mhz f osc 1.0 mhz or 1.6 mhz f osc 5.0 mhz the operating range for f osc can be set with bit 1 of system clock selection register 1 (ssr1: $027). 2. the oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. after v cc reaches 2.7 v at power-on. b. after reset input goes low when stop mode is cancelled. c. after stopc input goes low when stop mode is cancelled. to ensure the oscillation stabilization time at power-on or when stop mode is cancelled, reset or stopc must be input for at least a duration of t rc . when using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 3. refer to figure 84. 4. refer to figure 85. 5. refer to figure 86. 6. refer to figure 87.
hd404369 series 108 high-speed f osc = 8.5 mhz version ac characteristics (hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c; hd40a4364/hd40a4368/hd40a43612/hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c) item symbol pins min typ max unit test condition notes clock oscillation frequency f osc osc 1 , osc 2 0.4 4 5.0 mhz 1/4 system clock division ratio 1 0.4 4 8.5 mhz 2, 3 x1, x2 32.768 khz instruction cycle time t cyc 0.8 1 10 m s1 0.47 1 10 m s 2, 3 t subcyc 244.14 m s 32-khz oscillator, 1/8 system clock division ratio 122.07 m s 32-khz oscillator, 1/4 system clock division ratio oscillation stabilization time (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 4 oscillation stabilization time (ceramic oscillator) t rc osc 1 , osc 2 40 ms 4 x1, x2 2 s 4 external clock high width t cph osc 1 80ns 5 47 ns 3, 5 external clock low width t cpl osc 1 80ns 5 47 ns 3, 5 external clock rise time t cpr osc 1 20 ns 5 15 ns 3, 5 external clock fall time t cpf osc 1 20 ns 5 15 ns 3, 5 int 0 , int 1 , evnb high widths t ih int 0 , int 1 , evnb 2 t cyc / t subcyc 6 int 0 , int 1 , evnb low widths t il int 0 , int 1 , evnb 2 t cyc / t subcyc 6
hd404369 series 109 item symbol pins min typ max unit test condition notes reset low width t rstl reset 2 t cyc 7 stopc low width t stpl stopc 1 t rc 8 reset rise time t rstr reset 20 ms 7 stopc rise time t stpr stopc 20 ms 8 input capacitance c in all input pins except test, r1 and r2 15 pf f = 1 mhz, v in = 0 v test 15 pf f = 1 mhz, v in = 0 v 9 test 180 pf f = 1 mhz, v in = 0 v 10 r1, r2 30 pf f = 1 mhz, v in = 0 v notes: 1. when using the subsystem oscillator (32.768 khz), one of the following relationships for f osc must be applied. 0.4 mhz f osc 1.0 mhz or 1.6 mhz f osc 5.0 mhz the operating range for f osc can be set with bit 1 of system clock selection register 1 (ssr1: $027). 2. when using the subsystem oscillator (32.768 khz), one of the following relationships for f osc must be applied. 0.4 mhz f osc 1.0 mhz or 1.6 mhz f osc 8.5 mhz the operating range for f osc can be set with bit 1 of system clock selection register 1 (ssr1: $027). 3. v cc = 4.5 to 5.5v 4. the oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. after v cc reaches 2.7 v at power-on. b. after reset input goes low when stop mode is cancelled. c. after stopc input goes low when stop mode is cancelled. to ensure the oscillation stabilization time at power-on or when stop mode is cancelled, reset or stopc must be input for at least a duration of t rc . when using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 5. refer to figure 84. 6. refer to figure 85. 7. refer to figure 86. 8. refer to figure 87. 9. applies to the hd40a4364, hd40a4368, hd40a43612, and hd40a4369. 10. applies to the hd407a4369.
hd404369 series 110 serial interface timing characteristics (hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c; hd404364/HD404368/hd4043612/hd404369/hd40a4364/hd40a4368/hd40a43612/hd40a 4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) during transmit clock output item symbol pins min typ max unit test condition note transmit clock cycle time t scyc sck 1t cyc load shown in figure 89 1 transmit clock high width t sckh sck 0.4 t scyc load shown in figure 89 1 transmit clock low width t sckl sck 0.4 t scyc load shown in figure 89 1 transmit clock rise time t sckr sck 80 ns load shown in figure 89 1 transmit clock fall time t sckf sck 80 ns load shown in figure 89 1 serial output data delay time t dso so 300 ns load shown in figure 89 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 during transmit clock input item symbol pins min typ max unit test condition note transmit clock cycle time t scyc sck 1t cyc 1 transmit clock high width t sckh sck 0.4 t scyc 1 transmit clock low width t sckl sck 0.4 t scyc 1 transmit clock rise time t sckr sck 80 ns 1 transmit clock fall time t sckf sck 80 ns 1 serial output data delay time t dso so 300 ns load shown in figure 89 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. refer to figure 88.
hd404369 series 111 t cpr t cpf v cc ?0.5 v 0.5 v osc 1 t cph t cpl 1/f cp figure 84 external clock timing 0.8v cc 0.2v cc int 0 , int 1 , evnb t ih t il figure 85 interrupt timing reset t rstr t rstl 0.2v cc 0.8v cc figure 86 reset timing t stpr t stpl 0.8v cc 0.2v cc stopc figure 87 stopc timing
hd404369 series 112 0.7v cc 0.3v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.4 v v ?0.5 v cc v ?0.5 v (0.8v ) * cc 0.4 v (0.2v ) * sck so si note: * v cc ?0.5 v and 0.4 v are the threshold voltages for transmit clock output, and 0.8v cc and 0.2v cc are the threshold voltages for transmit clock input. cc cc t sckh figure 88 serial interface timing r l = 2.6 k w v cc hitachi 1s2074 or equivalent r = 12 k w test point c = 30 pf figure 89 timing load circuit
hd404369 series 113 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size for the hd404364, hd40a4364, HD404368, hd40a4368, hd4043612 and hd40a43612 as a 16-kword version (hd404369, hd40a4369). the 16-kword data sizes are required to change rom data to mask manufacturing data since the program used is for a 16-kword version. this limitation applies when using an eprom or a data base. vector address zero-page subroutine (64 words) pattern & program (4,096 words) not used vector address zero-page subroutine (64 words) pattern & program (12,288 words) not used rom 4-kword version: hd404364, hd40a4364 rom 12-kword version: hd4043612, hd40a43612 $0000 $000f $0010 $003f $0040 $0fff $1000 $3fff $0000 $000f $0010 $003f $0040 $2fff $3000 $3fff fill this area with 1s vector address zero-page subroutine (64 words) pattern & program (8,192 words) not used rom 8-kword version: HD404368, hd40a4368 $0000 $000f $0010 $003f $0040 $1fff $2000 $3fff
hd404369 series 114 hd404364/HD404368/hd4043612/hd404369/hd40a4364/hd40a4368/ hd40a43612/hd40a4369 option list please check off the appropriate applications and enter the necessary information. 3. rom code media date of order customer department name rom code name lsi number eprom: ceramic oscillator crystal oscillator external clock f = mhz f = mhz f = mhz 4. system oscillator (osc1, osc2) with 32-khz cpu operation, with time base for clock without 32-khz cpu operation, with time base for clock without 32-khz cpu operation, without time base 2. optional functions note: * options marked with an asterisk require a subsystem crystal oscillator (x1, x2). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 5 mhz operation 8.5 mhz operation 5 mhz operation 8.5 mhz operation 5 mhz operation 8.5 mhz operation 5 mhz operation 8.5 mhz operation hd404364 hd40a4364 HD404368 hd40a4368 hd4043612 hd40a43612 hd404369 hd40a4369 4-kword 8-kword 12-kword 16-kword 1. rom size dp-64s fp-64b fp-64a 6. package please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). used not used 5. stop mode * *
hd404369 series 115 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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